ispLEVER Classic Software

Design environment for Lattice CPLDs and mature programmable products.

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ispLEVER Classic is the design environment for Lattice CPLDs and mature programmable products. It can be used to take a Lattice device design completely through the design process, from concept to device JEDEC or Bitstream programming file output.

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Overview

The current version is ispLEVER Classic 2.1, released on December 30th, 2020.

ispLEVER Classic software is supported on the Windows 7, Windows Vista, or Windows XP or operating systems.

To design with other Lattice FPGA families, download the Lattice Diamond or iCEcube2 software. You can install and run Lattice Diamond, iCEcube2, and ispLEVER Classic concurrently.

Downloading and installing ispLEVER Classic

Follow the three steps below to Download, Install, and License ispLEVER Classic.

STEP 1 - Download

ispLEVER Classic consists of the modules as listed below; The ispLEVER Classic Base Module installation (which includes Synplify Synthesis module and Mentor ModelSim Lattice Edition for simulation) and the ispLEVER Classic FPGA Module installation.

Use the Downloads tab on this page to download the software installers.

Module Device Support / Feature Subscription License
ispLEVER Classic 2.1 Base Module:
This includes the ispLEVER Project Navigator, and all the tools and device libraries you need to implement a design for any of the programmable families listed at the right. It also includes the Lattice version of the Synplify™ Pro synthesis tool (I-2014.03LC) from Synopsys® for HDL synthesis as well as the Mentor ModelSim Lattice Edition.		 CPLD:
ispMACH 4000ZE/Z/V/B/C
ispMACH 5000VG
ispMACH 5000B
ispMACH 4A3/5
MACH4/5
ispXPLD 5000MX
ispLSI 8000
ispLSI 5000VE
ispLSI 2000VE
ispLSI 1000
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SPLD:
GAL and ispGAL

GDX:
ispGDXVA
ispGDX2
FPGA
ispXPGA
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ispLEVER Classic 2.1 FPGA Module:
This optional module adds support for ORCA FPGA and FPSC devices.
Note that the Base Module must be installed prior to the FPGA Module.		 FPGA:
ORCA FPGA
ORCA FPSC
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STEP 2 - Install each ispLEVER Classic Module

Starting with the ispLEVER Classic Base Module, unzip the downloaded file, then double-click the extracted file and to start the installation procedure. You can also download the installation guide from the Documentation tab on this page and read it for more detailed instructions and options.

For Windows 10 — Download and install the service pack enabling Windows 10 support. Please follow installation instructions in the readme.txt file within the installation download.

Licensing

STEP 3 - Purchase/Renew ispLEVER Classic License

The ispLEVER Classic license enables users to design and optimize solutions for CPLD and Legacy devices.

To purchase an ispLEVER Classic license, please go to the Online Store or contact a local sales representative or distributor.

If you have purchased a Software license and received a Software Serial Number, please go to our Subscription licensing form.

Version History

ispLEVER Classic 2.1

  • Replaced Aldec™ Active-HDL™ with Mentor® ModelSim® Lattice FPGA Edition. Active-HDL Lattice Edition is still supported but not included.

ispLEVER Classic 2.0

Lattice Synthesis Engine (LSE)

  • Support added for Mach4000 CPLD family. LSE will be selected for the synthesis tool, by default, for new projects targeting these families. Existing projects will continue to use the synthesis tool previously used by that project. For Mach4000 CPLD, user can switch between LSE and Synopsys Synplify Pro.

Aldec Active-HDL Simulation – updated version to 10.1

Software Downloads & Documentation

Quick Reference
Technical Resources
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
Generating a Schematic Symbol for OrCAD Capture
AN8075 9/1/2006 PDF 554.9 KB
Power Estimation in ispXPGA Devices (spreadsheet file)
This .zip contains the spreadsheet that is referenced in TN1043 		TN1043 5/1/2004 ZIP 31.8 KB
Power Estimation in ispXPGA Devices
Please note that a spreadsheet with built-in formulas is also available for use with TN1043, and available for download on this page. 		TN1043 1/1/2004 PDF 447.1 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
ispLEVER Classic 2.1 Installation Guide
2.1 12/30/2020 PDF 539.8 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Simulating Designs for Lattice FPGA Devices
This document explains how to use Synopsys® VCS®, Cadence® NCVerilog®, Cadence NC-VHDL®, and Aldec Riviera Pro® and Active-HDL® software to simulate designs that target Lattice Semiconductor FPGAs. (ispLEVER 6.x, 7.x) 		6/15/2007 PDF 111.5 KB
Schematic Entry Reference Manual
(ispLEVER Classic) 		11/24/2004 PDF 698 KB
ABEL Design Manual
(ispLEVER 4.x, 5.x, 6.x, Classic) 		3/1/2003 PDF 606.2 KB
ABEL-HDL Reference Manual
(ispLEVER 4.x, 5.x, 6.x, Classic) 		3/1/2003 PDF 1.4 MB
ispLSI Macro Library Reference Manual
Contains functional and pin descriptions of the schematic macros available in ispLEVER. (ispLEVER 4.x, 5.x, 6.x, Classic) 		8/1/2000 PDF 3.3 MB
FPGA Physical Design Rule Check (DRC) Desk Reference
Contains descriptions of design rule check warning and error messages you may encounter when running your FPGA designs in ispLEVER's Project Navigator. (ispLEVER 4.x, 5.x, 6.x, 7.x, 8.x) 		8.0 11/10/2009 PDF 102.9 KB
FPGA Design Guide
Includes comprehensive instructions on how to use the ispLEVER tools to design for Lattice FPGAs. (ispLEVER 8.0) 		8.0 11/10/2009 PDF 2.5 MB
Generic Macro Library Reference Guide
Contains functional and pin descriptions of the schematic "generic" macros available in ispLEVER Classic. Macros are compatible with ispMACH 4000 Family CPLDs. 		3/5/2018 PDF 461.7 KB
LSE for ispLEVER Classic User Guide
1.0 6/16/2015 PDF 245.7 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
PCN10A-11 Notification of Intent to Freeze ispLEVER After Version 8.2
Conversion 		PCN10A-11 1.0 7/25/2011 PDF 52.7 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Lattice OrCAD Capture Schematic Library (OLB)
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs. 		7.0 2/1/2021 ZIP 3.2 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Schematic and ABEL-HDL Design
How to design, simulate, implement, and verify a counter circuit targeted to a CPLD device. The design uses a top-level schematic and two lower-level ABEL-HDL modules. Tutorial Topics/Tools: CPLD Schematic and HDL Design Entry, CPLD Fitting, ispLEVER 		5/1/2006 PDF 2 MB
LSE for ispLEVER Classic 2.0 Tutorial
1.0 6/16/2015 PDF 372.7 KB
Using the ispXPGA Floorplanner
How to use the Floorplanner to locate elements, make pin and block assignments, and examine timing delay in a design targeted to an ispXPGA device. Tutorial Topics/Tools: Design Planning, ispLEVER, Floorplanner. (ispLEVER 4.x, 5.x, 6.x, Classic) 		5/1/2005 PDF 515.7 KB
HDL Synthesis Design with LeonardoSpectrum: CPLD Flow
How to use LeonardoSpectrum to synthesize a Verilog design for a Lattice CPLD device. Tutorial Topics/Tools: Logic Synthesis, ispLEVER, LeonardoSpectrum. (ispLEVER 4.x, 5.x, 6.x) 		5/1/2005 PDF 313 KB
HDL Synthesis Design with Synplify: CPLD Flow
How to use Synplify to synthesize a VHDL design for a Lattice CPLD device. Tutorial Topics/Tools: Logic Synthesis, ispLEVER, Synplify (ispLEVER 6.x) 		5/1/2005 PDF 446.1 KB
HDL Synthesis Design with Precision RTL: CPLD Flow
This tutorial shows you how to use Mentor Graphics Precision RTL Synthesis from within ispLEVER to synthesize a Verilog design and generate an EDIF file for a Lattice CPLD device. Tutorial Topics/Tools: Logic Synthesis, ispLEVER, Precision RTL 		5/1/2006 PDF 263.8 KB
HDL Synthesis Design with Synplify: ispXPGA Flow
How to use Synplify to synthesize a VHDL design for a Lattice ispXPGA device. Tutorial Topics/Tools: Logic Synthesis, ispLEVER, Synplify. 		5/1/2005 PDF 509.1 KB
HDL Synthesis Design with LeonardoSpectrum: ispXPGA Flow
How to use LeonardoSpectrum to synthesize a Verilog design for a Lattice ispXPGA device. Tutorial Topics/Tools: Logic Synthesis, ispLEVER, LeonardoSpectrum. (ispLEVER 4.x, 5.x, 6.x) 		5/1/2005 PDF 363.7 KB
Synthesis Data Flow Tutorial
This tutorial shows you how to use Synplicity Synplify® Pro for Lattice with ispLEVER® to synthesize a Verilog HDL design and to generate an EDIF file for a Lattice FPGA device. Tutorial Topics/Tools: FPGA logic synthesis, ispLEVER, Synplify. 		12/15/2008 PDF 314.3 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Active-HDL simulation libraries for ispLEVER Classic devices
Use these libraries if you wish to use ispLEVER Classic with Active-HDL Lattice Edition. 		10/19/2011 ZIP 81.6 MB
ispLEVER Classic 2.1 FPGA Module
2.1 12/30/2020 ZIP 350.8 MB
ispLEVER Classic 2.1 Base Module
2.1 12/30/2020 ZIP 786.8 MB
ispLEVER Classic 2.1 Service Pack for Windows 10
1.0 12/30/2020 ZIP 18.1 MB
PALtoGAL v3 12
Translates PAL JEDEC files to GAL JEDEC format. 		5/24/2001 ZIP 35.4 KB

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