The RISC-V RX and LPDDR4 Memory Controller Reference Design provides an example usage of the RISC-V RX soft IP and LPDDR4 memory controller in Lattice Avant™ and CertusPro™ NX FPGA devices.
The Lattice Semiconductor RISC-V RX CPU contains a 32-bit RISC-V processor core and several submodules – Platform Level Interrupt Controller (PLIC), Core Local Interrupter (CLINT), and Watchdog. The CPU core supports the RV32IMC instruction set and debug feature, which is JTAG – IEEE 1149.1 compliant. The modules outside are accessed by the processor core using AXI or Local Bus Interface.
The Lattice Semiconductor LPDDR4 Memory Controller IP Core provides a solution to interface with LPDDR4 SDRAM. Lattice provides a turnkey solution consisting of a controller, DDR PHY, and associated clocking and training logic. The LPDDR4 Memory Controller IP Core reduces the effort required to integrate a memory controller with user application designs. It minimizes the need to directly handle the LPDDR4 SDRAM signals by providing AXI4 interface support.
RISC-V RX CPU IP - The RISC-V RX CPU IP has AXI-based instruction and data ports. The instruction port is connected to the memory that contains the software code for CPU execution. The data port is connected to the memory and peripherals for control. The local UART feature is enabled to allow communication through serial protocol.
LPDDR4 Memory Controller IP - The LPDDR4 Memory Controller IP enables access to external LPDDR4 memory modules. The memory can be used to store CPU software code and data. The memory controller IP are different on CertusPro-NX and Lattice Avant.
AXI4 Interconnect IP - Used to connect the RISC-V RX instruction and data AXI ports (managers) to various subordinates within the system. This includes the system memory, LPDDR4 memory controller, SPI flash controller, and peripherals. The interconnect output interfaces are AXI-based. As such, conversion bridges are used when connecting the AXI4 Interconnect to AHB-Lite or APB-based subordinates.