​​Mutex IP Core​

​​Resolves Shared Resource Competition in Multi-Processor Environments​

The Lattice Semiconductor Mutex IP is used in multi-processor environment to solve the competition of the shared resources between different processors. The Mutex provides a configurable number of registers for processors to claim they gain exclusive access to particular resources, like shared memory space or shared peripherals.

Resource Utilization details are available in the IP Core User Guide.

Features
  • AXI-Lite interface and AHB-Lite interface
  • Configurable number of mutex
  • Configurable interface numbers
  • Configurable CPUID width to clarify the owner of mutex
  • Selectable hardware identification support

Block Diagram

Ordering Information

The Mutex IP is provided at no additional cost with the Lattice Propel design environment. The IP can be fully evaluated in hardware without requiring an IP license string

Documentation

快速参考
标题 编号 版本 日期 格式 文件大小
选择全部
Mutex IP - Lattice Propel Builder 2025.2 User Guide
FPGA-IPUG-02307 1.0 12/11/2025 PDF 955.4 KB
标题 编号 版本 日期 格式 文件大小
选择全部
Mutex IP - Lattice Propel Builder 2025.2 User Guide
FPGA-IPUG-02307 1.0 12/11/2025 PDF 955.4 KB