Lattice Radiant Version History

Radiant 2.2

  • Device Support:
    • CrossLink-NX Device Family (LIFCL)
      • 17K and 40K devices bitstream enabled.
    • Certus-NX Device Family (LFD2NX):
      • 40K (-7/-8/-9) HP/LP 1.0V (COM/IND) - CABGA196
      • 40K (-7/-8/-9) HP/LP 1.0V (COM/IND) - CSFBGA121
      • 40K devices bitstream enabled
  • Tool and Other Enhancements:
    • Programmer – Supports full encryption and authentication
    • Simulation tool change – Mentor ModelSim® is the new OEM simulation tool included with Radiant software. ModelSim replaces Aldec-Active HDL™.
              NOTE: For post-routing simulation, please use a full version of ModelSim PE. The OEM version will be addressed in an upcoming software release
    • Reveal – Reveal Analyzer/Controller support for CrossLink-NX (LIFCL) and Certus-NX device families.
    • Soft Error Injection – Soft Error Injection (SEI) Editor allows you to generate single-bit errors, insert them into a bitstream, and detect them for analysis, simulating the effect of radiation damage on the device’s configuration memory./li>

Radiant Update 2.1

  • Device Support:
    • Certus™-NX Device Family (LFD2NX) offers the following 40K device:
      • 40K (-7/-8/-9) HP/LP 1.0V (COM/IND) – Bitstream Disabled
        • CABGA256
      Note: Bitstream generation is disabled for CrossLink-NX devices for this release, but bitstream for LIFCL-40K is expected to be enabled in the upcoming Service Pack (Radiant 2.1 SP1).
  • Tool and Other Enhancements:
    • Physical Designer – The Physical Designer provides a central location where a user can do all the floor-planning and be able to view the physical layout of the design.
    • FPGA Libraries -- New Primitives:
      • CRE (LFD2NX) only. License controlled.)
      • FIFO16K
    • Pin Migration - This release adds Pin Migration support, allowing user to view devices that are of the same family and package as your current device and view incompatible pins.
    • Security – The LFD2NX device supports user mode Cryptographic Engine (CRE).
    • SystemVerilog Support – as follows:
      • Lattice Synthesis Engine – The ability to read and synthesize SystemVerilog.
      • File Hierarchy View – The ability to read and produce a hierarchical file view of design.
      • Hierarchy Viewer – The ability to read and produce hierarchical view in Design Constraint Editor, Netlist Analyzer, Floorplan View.
      • Reveal – support for SystemVerilog for Reveal Controller, Reveal Analyzer, and Reveal Inserter.

Radiant Update 2.0.1

  • Device Support:
    • CrossLink-NX™ Device Family offers new 17K devices and adds new 40K packages:
      • 17K (-7/-8/-9) HP/LP 1.0V (COM/IND) – Bitstream disabled
        • CABGA256
        • CSFBGA121
        • QFN72
        • WLCSP72
      • 40K (-7/-8/-9) HP/LP 1.0V (COM/IND)
        • CSFBGA121
        • CABGA256
  • Tool and Other Enhancements/Updates:
    • IP Evaluation for CrossLink-NX 40K devices – If you don’t have licenses for the soft intellectual properties (IPs) downloaded from “IP on Server,” you can evaluate these soft IPs for approximately four hours before the device resets itself.
    • New Foundation IPs - Four new foundation IPs are added:
      • 1D Filter
      • Adder Tree
      • Barrel Shifter
      • DSP_Mult_Mult_Accumulate
    • Programmer – Programmer has enhanced support for the Security features including Flash protection (128-bit device password) and AS-256 Encryption and Lock.
    • Security Tools (Key Generation) – A new Radiant Bitstream Security Setting tool has been added that allows you to generate and verify keys that are used for bitstream obfuscation. The GUI provides user entry for Flash protection (128-bit device password) and AES-256 Encryption.
    • sysCONFIG – A new attribute, CONFIGIO_VOLTAGE_BANK0/1, has been added for sysCONFIG.
    • Updated Radiant Tutorial for CrossLink-NX – An updated Tutorial has been added using the CrossLink-NX Evaluation Board.

Radiant 2.0

  • Device Support:
    • CrossLink-NX Device Family for the following packages:
      • 40K (-7/-8/-9) HP/LP 1.0V (COM/IND) - CABGA400
      • 40K (-7/-8/-9) HP/LP 1.0V (COM/IND) - CSBGA289
      • 40K (-7/-8/-9) HP/LP 1.0V (COM/IND) - QFN72
      The Lattice Radiant Software Guide for Lattice Diamond Users has been enhanced to help users to migrate their designs to CrossLink-NX devices using the Radiant software. Users with designs on such Lattice devices as CrossLink and ECP5, designed using Lattice Diamond software, can use this guide to quickly grasp concepts of the new features of CrossLink-NX devices and designing with the Radiant software.
  • Tool and Other Enhancements:
    • Device Constraint Editor – Updates and enhancements have been added to Device Constraint Editor.
    • ECO Editor – A new Radiant software tool has been added that supports interactive Engineering Change Order (ECO) editing.
    • Floorplan View – Updates and enhancements have been added to Floorplan View. Updates include a new I/O placement feature that is used for I/O assignment such as DDR interface, DQS and clock assignments.
    • IP Catalog – Updates and enhancements have been added to Modules.
    • Power Calculator – Updates and enhancements have been added to support CrossLink-NX devices.
    • Propagation of IP Constraints – Radiant software now supports hierarchical constraints in IP applications and writes a new constraint file to propagate lower level constraints to top level under predefined constraint design rules.
    • Reveal Controller – A new Radiant software tool has been added for the CrossLink-NX family to create virtual control switches/LEDs; reading/writing to bank of registers/memory; and read/write access to control and status registers of PLL, I2C/FIFO, DPHY, CDR and PCIe hard-IPs.
    • Run Manager – A new Radiant software tool has been added that is used to run multiple synthesis and place and route passes, compare the results of multiple implementations for further analysis to get best solutions.
    • Source Templates – New CrossLink-NX templates have been added for both Verilog and VHDL in Source Template. In Source Template Editor, see:
      • Verilog > Primitive Templates > lifcl Primitive
      • VHDL > Primitive Templates > lifcl Primitive
    • Simultaneous Switching Outputs (SSO) Calculator – A new Radiant software tool has been added that estimates Simultaneous Switching Noise (SSN) affecting a victim pin according to the switching characteristics of aggressor pins.
    • Timing Constraint Editor – Updates and enhancements have been added to Timing Constraint Editor.

Radiant 1.1

  • 针对iCE40 UltraPlus器件的增强和错误修复
    • 新增HDL属性RGB_TO_GPIO。
    • 新增四个iCE40 UltraPlus位流策略选项:
      • 暖启动(Warm Boot)
      • 将所有未使用的IO设置为不上拉
      • 设置NVCM安全性
      • SPI闪存低功耗模式
  • 优化IP工具和流程
  • Constraints Syntax and Flow更新
    • 时序约束:新增支持对象访问指令(Object Access Command (-of_objects) ),让对象访问更灵活高效。注意:该选项仅在Radiant 1.1软件的约束文件中可用。图像用户界面(GUI)预计将在Radiant 1.2中支持该选项。
    • 物理约束:在ldc_prohibit约束中新增支持-region选项。在ldc_set_location中也支持该选项。
    • 时序约束编辑器
      • 新增set_load约束
      • 新增Disable/Enable复选框,方便停用或使用约束。
  • 工具及其他升级
    • 根据时序报告交叉探索时序路径。Map和PAR时序报告现添加了超链接,用户可以在Netlist Analyzer、Physical View和Floorplan View中查看时序路径。
    • 工具窗口可拖拽。现在所有的工具和视图都可以分离合并,用户可以在Radiant软件以外的环境中使用这些工具。
    • 莱迪思综合引擎(LSE)。LSE在Radiant 1.0的基础上性能有很大提升:
      • 优化嵌入式块存储器(Embedded Block RAM, EBR)、有限状态机(FSM)以及数字信号处理器提取。
      • 优化局部实现(Area implementation)和运行时间。
    • 功耗评估器。新增了独立运行的功耗评估器。
    • 仿真向导程序(Simulation Wizard)。更新了仿真向导程序,现支持综合后仿真。
    • 源代码模板(Source Template)。 新增了源代码模板标签,无需运行Source Editor即可方便获取各类模板。优化了模板的选择。可用的VHDL和Verilog模板包括:
      • 通用模板
      • PMI模板
      • Primitive模板
      • 属性模板
      • 加密模板/li>
      • 时序约束
      • 物理约束
    • Ubuntu操作系统。新增支持Ubuntu操作系统LTS 16.4系列版本。

Radiant 1.0 SP1

  • 如果用户在其设计中使用LVDSE IO类型,则需要使用该Service Pack重新编译。
  • 如果LSE综合报告文件的Area Report中出现CCU2 Primitive, 有可能会因为进位链优化而出现不正确的综合结果。建议使用此Service Pack重新编译设计,避免出现模拟和/或硬件运行失败。该方法仅适用于LSE。
  • 修复了其他几个重大的客户问题,解决了时序引擎中与映射、布局、布线相关的不稳定问题。

Radiant 1.0

  • 采用常见的SDC格式对时序和物理约束进行标准化,帮助您在设计中轻松应用约束。
  • 统一的从综合到布局布线的静态时序分析,以加速设计时序收敛。
  • 优化了IP 安全流程和环境,实现软IP的有效分发,提高了第三方软IP的安全性。
  • 全新简化的GUI设计,可选择亮色或深色主题。
  • 精简高效的设计流程和工具,提高了易用性。
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