莱迪思Radiant版本历史记录

Radiant Update 2023.2.1

  • Device Support:
    • CertusPro™-NX (LFCPNX)
      • 50K (-9/-8/-7) 1.0V (AUTO) – ASG256, CBG256, BFG484.
  • Tool and Other Enhancements:
    • Primitives
      • OUTDELAYC primitive has been added for CertusPro-NX device.
    • Device Constraint Editor
      • 75Mhz selection has been added for MCCLK_FREQ.
    • MAP – DRC errors regarding shared configuration pin usage for Nexus devices have been resolved.
    • Timing Data – DPHY timing arcs to fix unconstrained path have been updated for Nexus device.
    • Reveal
      • JTAGhub feature modules have been enhanced for Nexus and Avant devices.
      • Pooling of data while SEDC is running has been enhanced for Reveal Controller and Reveal Analyzer.
    • Hardware Data File
      • Minimum pulse width (MPW) has been aligned with datasheet for CrossLink-NX device.
      • Correlation for CertusPro-NX (LFCPNX) IBIS Model has been resolved.

Radiant 2023.2

  • Device Support:
    • Lattice Avant™ (LAV-AT)
      • E70 (-1/-2/-3) 0.82V (COM/IND) – LFG676, LFG1156
        • 500E has been renamed to E70.
    • CrossLink™-NX (LIFCL)
      • 33U (-7/-8) 1.00V (COM/IND) – FCCSP104
      • 33U (-8) 1.00V (COM/IND) – WLCSP84
  • Tool and Other Enhancements:
    • Device Selector – The device information of the LAV-AT device (E70) has been updated to add 637000 System Logic Cells (LCs).
    • Lattice Synthesis Engine (LSE) – LSE now supports the LAV-AT device.
    • Foundation IP – LAV-AT-E design needs to be re-generated for the Foundation IP/Soft IP. You also need to re-compile the design and re-generate the bitstream.
    • Primitives – The following primitives have been added for the LAV-AT device:
      • DDRPHY64C and DDRPHY72C
      • DDRPHY16D, DDRPHY32D, and DDRPHY64D
      • DDRPHY16E, DDRPHY32E, and DDRPHY64E
      • CONFIG_DONE and CONFIG_LMMIC
      • ECLKDIVA and ECLKSYNCA
      • OSCE
    • GPIO Pins – For the LAV-AT device, each HPIO banks now have 1 EXT_RES dedicated pins.
    • IBIS Models – IBIS has been enhanced to include sysCONFIG pins for the LAV-AT device.
    • Third-Party Simulation Tools – Cadence Xcelium and Synopsys VCS now support the LAV-AT device.
    • MAP – For all Nexus devices, mapper issues DRC if ECLKSYNC is missing from the ECLKDIV input.
    • Place & Route Timing Analysis – Running PAR Timing Analysis is now required for Nexus devices.
    • Static Timing Analyzer (STA) – The STA introduces automated multi-corner Static Timing Analysis reporting to all Nexus devices which eliminates manual operations.
      • While the PAR report includes multi-corner timing, it is recommended to run STA and analyze the timing results at each corner in the STA timing report.
    • CDC Register – The CDC_register attribute allows you to constrain CDC (Clock Domain Crossing) synchronization registers for placement and timing analysis.
    • SEI Editor – The multi-bit (2-bit) error option has been added to the SEI Editor for all Nexus devices.
    • Programmer
      • To enable a robust Dual Boot and Ping-Pong functionality, the bitstream of LFMXO5-25, LFMXO5-55T, and LFMXO5-100T devices with embedded flash memory needs to be re-generated.
      • Deployment Tool now allows adding user data while generating Dual Boot and Ping-Pong features.
    • Strategies – The default value of the GSR Infer strategy has been changed to “OFF” for Synplify, LSE, and MAP.
    • Block-Based Design – The Exclusive option has been added to Physical Designer for reused macros.
    • IP Generator – The IP Generator has been enhanced to be able to provide VHDL top-level file capability.
    • License File – The TS_OK option has been enabled for Radiant subscription license. This option allows you to run the Radiant software on a remote connection.
    • File List – In File List View, you can now manually set top-level modules by right-clicking on an input file.
    • Inclusive Language – Radiant documentation has been partially updated to follow Lattice’s Inclusive Language guidelines.
      • The following terms have been updated:
        • Master SPI has been changed to Controller SPI.
        • Slave SPI has been changed to Target SPI.
    • Simulation Wizard
      • Simulation Wizard now supports the "-t" option. This option has been added to specify the time resolution of the simulator for VHDL resolution in mixed-language simulations.
      • The “sim_generate_script” Tcl command has been added for Simulation Wizard. You can use this command to generate any file types from your current Radiant project.
    • TCL Enhancement – New Tcl commands have been added to support project and non-project flows.
      • STA Tcl commands have been added allowing you to query the timing database and generate timing reports or data without having to recompile the design.
    • Test Fixture Template – The GSR instance has been added to the Test Fixture Template for Avant and Nexus devices.

Radiant Update 2023.1.1

  • Tool and Other Enhancements:
    • PLL Foundation IP – The Fractional-N settings were updated to improve PLL design stability for all Nexus devices.

Radiant 2023.1

  • Device Support:
    • MachXO5™-NX (LFMXO5)
      • 55T (-7/-8/-9) 1.00V (COM/IND) – BBG400
      • 100T (-7/-8/-9) 1.00V (COM/IND) – BBG400
  • Tool and Other Enhancements:
    • Block-Based Design – The Block-Based Design feature has been added to the Radiant software. This new feature allows you to implement macros in your project, including the ability to export macros and reuse them in other designs.
    • Message Classification – The “Critical Warning” message severity level has been added to the Radiant software. This severity level pertains to issues that could result in a functional problem.
    • Multi-thread Route – The multi-thread route has been added to the Radiant software for the Avant device. You can now run PAR in multi-thread mode by using the "-exp maxThreads=n" command. The default number of threads in the Avant device is 4, and the maximum is 8.
    • Place & Route Timing Analysis – The Place & Route Timing Analysis process has been updated for Avant and other devices. Running PAR Timing Analysis is required for Avant, while it is optional for other devices.
    • Programmer – Support for MachXO3D and LFMNX devices have been added to the Programmer tool.
    • Reports View – The Constraint Checker Report section has been added to the Synthesis Reports tab of the Radiant software. This section is only visible when Synplify Pro is used.
    • Reveal Controller – The implementation of Reveal Controller for Hard IPs has been updated for Radiant 2023.1.
    • Revision Control – Radiant will now output a list of files that are recommended to be placed under revision control for the current project.
    • Strategies – The Command Line Option strategy has been added to Place & Route Timing Analysis to enable the false_path constraint for timing constraints coverage.
    • sysCONFIG Settings – With this update, at least one of JTAG_PORT, SLAVE_SPI_PORT, SLAVE_I2C_PORT, or SLAVE_I3C_PORT must be enabled for Nexus devices. Otherwise, Map reports a DRC error.
    • Synthesis Tool – The default synthesis tool for new projects has been changed to Synplify Pro.
    • Timing Analysis Report – The Timing Analysis Report has been updated for the Avant device. The DELAYB calculation is now included in the data path.
    • Timing Data – The IOLOGIC GBB timing data for the CertusPro-NX device has been updated for Radiant 2023.1.

Radiant Update 2022.1.1

  • Device Support:
    • CertusPro™-NX (LFCPNX)
      • 50K (-7/-8/-9) 1.00V (COM/IND) – ASG256
      • 50K (-7/-8/-9) 1.00V (COM/IND) – BBG484
      • 50K (-7/-8/-9) 1.00V (COM/IND) – BFG484
      • 50K (-7/-8/-9) 1.00V (COM/IND) – CBG256
  • Tool and Other Enhancements:
    • Power Calculator – The Power Calculator for CertusPro-NX (LFCPNX) has been updated to reflect a roughly 10% improvement (lower power consumption) for designs using PCIe over previous versions due to improved silicon correlation data.
    • Reveal Logic Controller/Analyzer – The Reveal User Status and User Control Register features have been updated to expand the values of the control and status signals to 32-address locations with a maximum data-width of 8 bits.
    • Simulation Library – The Simulation Library has been updated to include compilation of PMI and source libraries.

Radiant 2022.1

  • Device Support:
    • Lattice Avant™ (LAV-AT-E)
      • 500K (-1/-2/-3) 0.82V (COM/IND) – LFG676
      • 500K (-1/-2/-3) 0.82V (COM/IND) – LFG1156
      • GSR is not available for the LAV-AT-E device.
    • The license maintenance number has been updated to support the current Radiant software’s version number. Please visit the Lattice Software Licensing page to request for a new license. To check the license maintenance number, open the Radiant license file located in ..\<install_directory>\license.
    • CrossLink™-NX (LIFCL)
      • SGMIICDR primitive is not supported in LIFCL (40K/17K) WLCSP72 and QFN72 packages.
      • The -7 speed grade option has been removed from the LIFCL-33 device.
  • Tool and Other Enhancements:
    • FPGA Libraries – The FPGA Library Guide has been updated to include the LAV-AT-E device.
    • Netlist Analyzer – The Netlist Analyzer tool now supports post-synthesis schematic view for Synplify Pro.
    • PAD Specification File – The PAD report has been updated to include the complete IO properties information of device families.
    • PLL Foundation IP – The PLL parameter calculation script has been updated to optimize the tuning algorithm for all devices except the iCE40UP and LAV-AT-E device.
    • Pre-Synthesis Constraint Editor (previously Timing Constraint Editor) – The Pre-Synthesis Constraint Editor tool has been updated to support the set_max_skew constraint for the Radiant 2022.1 software.
    • Programmer – The Programmer tool has been updated to support the LAV-AT-E device.
    • Project Navigator – The Message Promotion/Demotion option has been added to Project > Message Promotion/Demotion. This new feature allows you to use TCL commands to promote/demote a message if you do not want it to be visible in non-GUI mode.
    • Reports
      • The MAP Resource Usage section has been updated to display the Logic, Distributed RAM, and RIPPLE Logic information of the project.
      • Constraint Propagation section has been added to Synthesis Reports.
      • Constraint Summary has been added to the Post-Synthesis and MAP Reports.
    • Timing Analysis Reports – The Timing Analysis Reports format has been updated to include the following sections:
      • The “Setup at User Specified Speed Grade Corner at Minimum Degrees” section has been added to the PAR Timing Analysis Report for the LAV-AT-E device.
      • A new command line parameter -dump_uncovered has been added for the PAR Timing Analysis Report. This results in timing dumping connections that are not covered in the uncoveredConn.log file.
    • Reveal Logic Controller/Analyzer
      • The User Memory, User Control, and User Register options have been added to the Reveal Logic Controller/Analyzer tool.
      • The Reveal Controller tool has been updated to add the simulation model feature.
      • For the LAV-AT-E device, adding the PAR Strategy command line option, “-exp WARNING_ON_PCLKPLC1=1” when using Reveal and JTAGH25 is required to avoid errors.
    • SSO Calculator – The SSO Calculator has been updated to support the LAV-AT-E device.
    • Synthesis Tool – The Synthesis default option has been added to Tool > Options. In the dropdown menu, you can choose between Lattice LSE or Synplify Pro.

Radiant Update 3.2.1

  • Device Support:
    • CertusPro™-NX (LFCPNX)
      • 100K (-7/-8) HP/LP 1.0V (AUTO) – ASG256
      • 100K (-7/-8) HP/LP 1.0V (AUTO) – BBG484
      • 100K (-7/-8) HP/LP 1.0V (AUTO) – CBG256

Radiant 3.2

  • Device Support:
    • MachXO5™-NX (LFMXO5)
      • 25K (-7/-8/-9) HP/LP 1.0V (COM/IND) – BBG256
      • 25K (-7/-8/-9) HP/LP 1.0V (COM/IND) – BBG400
    • CrossLink™-NX (LIFCL)
      • 33K (-7/-8) HP/LP 1.0V (COM) – WLCSP84
      • 33K (-8) HP/LP 1.0V (IND) – WLCSP84
  • Tool and Other Enhancements:
    • License Debugger – The License Debug tool now displays all Network Feature Card (NIC) IDs. A direct link to LmTools has also been added to access the license server.
    • Power On Reset (POR) Debug – This new feature has been added to the Reveal Analyzer/Controller tool for the Radiant 3.2 software.
    • Programmer, Reveal Logic Analyzer/Controller, SEI Editor
      • These tools have been updated to support the MachXO5-NX (LFMXO5) and CrossLink-NX (LIFCL-33) devices with bitstream generation capability and full encryption/ authentication.
      • Added I3C Bridge support to Programmer.
    • Radiant File Type Support – The "Force File Type" option has been added to the “Add Existing File” dialog box. This new feature allows users to change their file types to Verilog or VHDL.
    • Radiant Project File – The Radiant Project (.rdf) file has been updated to include the Radiant version number.
    • Simulation Wizard – The Simulation Wizard tool has been updated. Users can now specify the simulation run length if the “Run simulation” option is selected.
    • Timing Analyzer – The “-datapath_only” option has been added to the set_max_delay constraint

Radiant 3.1.1 MachXO5-NX Device Update

  • Device Support:
    • MachXO5™-NX (LFMXO5)
      • 25k (-7/-8/-9) HP/LP 1.0 V (COM/IND) – BBG256
      • 25k (-7/-8/-9) HP/LP 1.0 V (COM/IND) – BBG400
  • Tool and Other Enhancements:
    • Programmer – The Programmer tool has been updated to support the MachXO5-NX (LFMXO5) device with plain bitstream only, no security or encryption features.
    • Reveal Logic Analyzer – The Reveal Logic Analyzer tool has been updated to support the MachXO5-NX (LFMXO5) device.
    • Update installer allows user to specify installation path – The user can specify the installation path when installing the MachXO5-NX Device Update

Radiant Update 3.1.1

  • Device Support:
    • CertusPro™-NX (LFCPNX)
      • 100K (-7/-8/-9) HP/LP 1.0 V (COM/IND) – BFG484
      • 100K (-7/-8/-9) HP/LP 1.0 V (COM/IND) – CBG256
      • Available under subscription licensing
    • Certus™-NX-RT (UT24C)
      • 40K (-7) HP/LP 1.0 V (AUTO) – CABGA256 is license controlled
    • CertusPro™-NX-RT (UT24CP)
      • 100K (-8) HP/LP 1.0 V (IND) – BBG484 is license controlled
  • Tool and Other Enhancements:
    • Radiant Device Selector – UT24C and UT24CP OPNs (Ordering Part Number) have been added to the Device Selector for the RT (Radiation Tested) Devices.

Radiant 3.1

  • Device Support:
    • Certus™-NX Auto Device PSR (LFD2NX)
  • Tool and Other Enhancements:
    • Device Constraint Editor – The default configuration of JTAG_PORT, DONE_PORT, INITN_PORT, and PROGRAMN_PORT has been set to “ENABLE.”
    • IO Eye-Opening Monitor (IO EOM) – The IO EOM feature has been added to the Reveal Analyzer/Controller tool for devices with PCS hard IP such as LFCPNX device family.
    • IP Encryption Flow – Improved protection for IEEE1735 compliant IP Encryption Flow.
    • IP Packager – The IP Packager tool has been updated. Radiant software now uses the Propel software version of IP Packager.
    • JTAG Debug – This new feature has been added to support simultaneous debugging of processor system and Reveal hardware debugging.
    • Standalone Timing Analyzer – This new feature can be used to run experimental timing analysis on designs using post-synthesis, post-map, post-PAR Unified Design Database (.udb), and associated timing constraints specified in the .pdc file of the design. The Standalone Timing Analyzer content has been added to the Radiant Software Help.
    • VHC File Extension Support – This release of the Radiant software adds the ability to recognize files with the .vhc file extension as VHDL files. VHC files inherit the same characteristics as .vhd (VHDL) files.
    • Virtual IO Ports Support – This new feature allows easy timing/resource estimation for over exceeding IO designs. A “Virtual” column has also been added to the Device Constraint Editor.

Radiant 3.0

  • Device Support:
    • CertusPro™-NX Device Family (LFCPNX):
      • 100K (-7/-8/-9) HP/LP 1.0V (COM/IND) - ASG256
      • 100K (-7/-8/-9) HP/LP 1.0V (COM/IND) - BBG484
      • 100K (-7/-8/-9) HP/LP 1.0V (COM/IND) - LFG672
      • 100K devices bitstream enabled
  • Tool and Other Enhancements:
    • Device Selector – When creating a new project in the Radiant software, the Device Selector now defaults to LICFL (CrossLink-NX), Performance Grade: 9_High-Performance_1.0 V, Part Number: LICFL-17-9BG256C. Also, the Device Selector now shows both device Part Name and device Family Name in the Family list. For example: LIFCL (CrossLink-NX).
    • FPGA Libraries – FPGA Libraries have been added for the CertusPro-NX Device Family (LFCPNX).
    • License Debug – Added license debug capability to specify the location of the license file and show the features that are available with the license in the Help > License Debug menu.
    • Security Settings Tool – The Security Settings Tool now supports .pem and .der file formats.
    • Signal Traceability – This new feature allows you to trace signals from Report View and Output Window and display signals in Netlist Analyzer.
    • Tutorial – The Lattice Radiant 3.0 Tutorial with CrossLink-NX (LIFCL) adds support for the newest CrossLink-NX Evaluation Board, Revision B. Tasks for programming the chip and for on-board logic analysis have been added.
    • Unified Constraints and Timing Analysis Flow – Pre-synthesis Timing Constraints Editor now works for both Lattice Synthesis Engine (LSE) and Synplify Pro.

Radiant Update 2.2.1

  • Device Support:
    • CrossLink-NX Automotive Devices (LIFCL):
      • 17K (-7) HP/LP 1.0V – CSFBGA121
      • 17K (-7) HP/LP 1.0V – CABGA256
      • 40K (-7) HP/LP 1.0V – CSFBGA121
      • 40K (-7) HP/LP 1.0V – CABGA256
      • 17K and 40K devices bitstream enabled.
    • CrossLink-NX (LIFCL) & Certus-NX (LFD2NX) PSR for C/I
  • Tool and Other Enhancements:
    • Power Calculator – Updates have been added to I/O, MIPIDPHY, and PCIE.
    • Mentor ModelSim Lattice Edition – ModelSim Lattice Edition has been updated to Revision 2021.02

Radiant 2.2

  • Device Support:
    • CrossLink-NX Device Family (LIFCL)
      • 17K and 40K devices bitstream enabled.
    • Certus-NX Device Family (LFD2NX):
      • 40K (-7/-8/-9) HP/LP 1.0V (COM/IND) - CABGA196
      • 40K (-7/-8/-9) HP/LP 1.0V (COM/IND) - CSFBGA121
      • 40K devices bitstream enabled
  • Tool and Other Enhancements:
    • Programmer – Supports full encryption and authentication
    • Simulation tool change – Mentor ModelSim® is the new OEM simulation tool included with Radiant software. ModelSim replaces Aldec-Active HDL™.
              NOTE: For post-routing simulation, please use a full version of ModelSim PE. The OEM version will be addressed in an upcoming software release
    • Reveal – Reveal Analyzer/Controller support for CrossLink-NX (LIFCL) and Certus-NX device families.
    • Soft Error Injection – Soft Error Injection (SEI) Editor allows you to generate single-bit errors, insert them into a bitstream, and detect them for analysis, simulating the effect of radiation damage on the device’s configuration memory./li>

Radiant 2.1

  • Device Support:
    • Certus™-NX Device Family (LFD2NX) offers the following 40K device:
      • 40K (-7/-8/-9) HP/LP 1.0V (COM/IND) – Bitstream Disabled
        • CABGA256
      Note: Bitstream generation is disabled for CrossLink-NX devices for this release, but bitstream for LIFCL-40K is expected to be enabled in the upcoming Service Pack (Radiant 2.1 SP1).
  • Tool and Other Enhancements:
    • Physical Designer – The Physical Designer provides a central location where a user can do all the floor-planning and be able to view the physical layout of the design.
    • FPGA Libraries -- New Primitives:
      • CRE (LFD2NX) only. License controlled.)
      • FIFO16K
    • Pin Migration - This release adds Pin Migration support, allowing user to view devices that are of the same family and package as your current device and view incompatible pins.
    • Security – The LFD2NX device supports user mode Cryptographic Engine (CRE).
    • SystemVerilog Support – as follows:
      • Lattice Synthesis Engine – The ability to read and synthesize SystemVerilog.
      • File Hierarchy View – The ability to read and produce a hierarchical file view of design.
      • Hierarchy Viewer – The ability to read and produce hierarchical view in Design Constraint Editor, Netlist Analyzer, Floorplan View.
      • Reveal – support for SystemVerilog for Reveal Controller, Reveal Analyzer, and Reveal Inserter.

Radiant Update 2.0.1

  • Device Support:
    • CrossLink-NX™ Device Family offers new 17K devices and adds new 40K packages:
      • 17K (-7/-8/-9) HP/LP 1.0V (COM/IND) – Bitstream disabled
        • CABGA256
        • CSFBGA121
        • QFN72
        • WLCSP72
      • 40K (-7/-8/-9) HP/LP 1.0V (COM/IND)
        • CSFBGA121
        • CABGA256
  • Tool and Other Enhancements/Updates:
    • IP Evaluation for CrossLink-NX 40K devices – If you don’t have licenses for the soft intellectual properties (IPs) downloaded from “IP on Server,” you can evaluate these soft IPs for approximately four hours before the device resets itself.
    • New Foundation IPs - Four new foundation IPs are added:
      • 1D Filter
      • Adder Tree
      • Barrel Shifter
      • DSP_Mult_Mult_Accumulate
    • Programmer – Programmer has enhanced support for the Security features including Flash protection (128-bit device password) and AS-256 Encryption and Lock.
    • Security Tools (Key Generation) – A new Radiant Bitstream Security Setting tool has been added that allows you to generate and verify keys that are used for bitstream obfuscation. The GUI provides user entry for Flash protection (128-bit device password) and AES-256 Encryption.
    • sysCONFIG – A new attribute, CONFIGIO_VOLTAGE_BANK0/1, has been added for sysCONFIG.
    • Updated Radiant Tutorial for CrossLink-NX – An updated Tutorial has been added using the CrossLink-NX Evaluation Board.

Radiant 2.0

  • Device Support:
    • CrossLink-NX Device Family for the following packages:
      • 40K (-7/-8/-9) HP/LP 1.0V (COM/IND) - CABGA400
      • 40K (-7/-8/-9) HP/LP 1.0V (COM/IND) - CSBGA289
      • 40K (-7/-8/-9) HP/LP 1.0V (COM/IND) - QFN72
      The Lattice Radiant Software Guide for Lattice Diamond Users has been enhanced to help users to migrate their designs to CrossLink-NX devices using the Radiant software. Users with designs on such Lattice devices as CrossLink and ECP5, designed using Lattice Diamond software, can use this guide to quickly grasp concepts of the new features of CrossLink-NX devices and designing with the Radiant software.
  • Tool and Other Enhancements:
    • Device Constraint Editor – Updates and enhancements have been added to Device Constraint Editor.
    • ECO Editor – A new Radiant software tool has been added that supports interactive Engineering Change Order (ECO) editing.
    • Floorplan View – Updates and enhancements have been added to Floorplan View. Updates include a new I/O placement feature that is used for I/O assignment such as DDR interface, DQS and clock assignments.
    • IP Catalog – Updates and enhancements have been added to Modules.
    • Power Calculator – Updates and enhancements have been added to support CrossLink-NX devices.
    • Propagation of IP Constraints – Radiant software now supports hierarchical constraints in IP applications and writes a new constraint file to propagate lower level constraints to top level under predefined constraint design rules.
    • Reveal Controller – A new Radiant software tool has been added for the CrossLink-NX family to create virtual control switches/LEDs; reading/writing to bank of registers/memory; and read/write access to control and status registers of PLL, I2C/FIFO, DPHY, CDR and PCIe hard-IPs.
    • Run Manager – A new Radiant software tool has been added that is used to run multiple synthesis and place and route passes, compare the results of multiple implementations for further analysis to get best solutions.
    • Source Templates – New CrossLink-NX templates have been added for both Verilog and VHDL in Source Template. In Source Template Editor, see:
      • Verilog > Primitive Templates > lifcl Primitive
      • VHDL > Primitive Templates > lifcl Primitive
    • Simultaneous Switching Outputs (SSO) Calculator – A new Radiant software tool has been added that estimates Simultaneous Switching Noise (SSN) affecting a victim pin according to the switching characteristics of aggressor pins.
    • Timing Constraint Editor – Updates and enhancements have been added to Timing Constraint Editor.

Radiant 1.1

  • 针对iCE40 UltraPlus器件的增强和错误修复
    • 新增HDL属性RGB_TO_GPIO。
    • 新增四个iCE40 UltraPlus位流策略选项:
      • 暖启动(Warm Boot)
      • 将所有未使用的IO设置为不上拉
      • 设置NVCM安全性
      • SPI闪存低功耗模式
  • 优化IP工具和流程
  • Constraints Syntax and Flow更新
    • 时序约束:新增支持对象访问指令(Object Access Command (-of_objects) ),让对象访问更灵活高效。注意:该选项仅在Radiant 1.1软件的约束文件中可用。图像用户界面(GUI)预计将在Radiant 1.2中支持该选项。
    • 物理约束:在ldc_prohibit约束中新增支持-region选项。在ldc_set_location中也支持该选项。
    • 时序约束编辑器
      • 新增set_load约束
      • 新增Disable/Enable复选框,方便停用或使用约束。
  • 工具及其他升级
    • 根据时序报告交叉探索时序路径。Map和PAR时序报告现添加了超链接,用户可以在Netlist Analyzer、Physical View和Floorplan View中查看时序路径。
    • 工具窗口可拖拽。现在所有的工具和视图都可以分离合并,用户可以在Radiant软件以外的环境中使用这些工具。
    • 莱迪思综合引擎(LSE)。LSE在Radiant 1.0的基础上性能有很大提升:
      • 优化嵌入式块存储器(Embedded Block RAM, EBR)、有限状态机(FSM)以及数字信号处理器提取。
      • 优化局部实现(Area implementation)和运行时间。
    • 功耗评估器。新增了独立运行的功耗评估器。
    • 仿真向导程序(Simulation Wizard)。更新了仿真向导程序,现支持综合后仿真。
    • 源代码模板(Source Template)。 新增了源代码模板标签,无需运行Source Editor即可方便获取各类模板。优化了模板的选择。可用的VHDL和Verilog模板包括:
      • 通用模板
      • PMI模板
      • Primitive模板
      • 属性模板
      • 加密模板/li>
      • 时序约束
      • 物理约束
    • Ubuntu操作系统。新增支持Ubuntu操作系统LTS 16.4系列版本。

Radiant 1.0 SP1

  • 如果用户在其设计中使用LVDSE IO类型,则需要使用该Service Pack重新编译。
  • 如果LSE综合报告文件的Area Report中出现CCU2 Primitive, 有可能会因为进位链优化而出现不正确的综合结果。建议使用此Service Pack重新编译设计,避免出现模拟和/或硬件运行失败。该方法仅适用于LSE。
  • 修复了其他几个重大的客户问题,解决了时序引擎中与映射、布局、布线相关的不稳定问题。

Radiant 1.0

  • 采用常见的SDC格式对时序和物理约束进行标准化,帮助您在设计中轻松应用约束。
  • 统一的从综合到布局布线的静态时序分析,以加速设计时序收敛。
  • 优化了IP 安全流程和环境,实现软IP的有效分发,提高了第三方软IP的安全性。
  • 全新简化的GUI设计,可选择亮色或深色主题。
  • 精简高效的设计流程和工具,提高了易用性。