LCD Controller - WISHBONE Compatible

Reference Design LogoThis reference design provides a processor interface to the common dot-matrix LCD module. The on-chip oscillator available on some Lattice CPLD or FPGA families can further simplify the implementation by eliminating the need for an external clock source. This design is also suitable for low-power applications together with Lattice zero-power CPLDs.

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Block Diagram

LCD Controller - WISHBONE Compatible

Performance and Size

Tested Devices* Language Performance I/O Pins Design Size Revision
iCE40-LP1K-CM121 VHDL clk_i > 50 MHz 26 67 LUTs 1.2
LCMXO2-1200HC-4TG100C Verilog clk_i > 50 MHz 33 25 LUTs 1.2
LCMXO2-1200HC-4TG100C VHDL clk_i > 50 MHz 33 25 LUTs 1.2
LCMXO2280C-3FT256C Verilog clk_i > 50 MHz 33 23 LUTs 1.2
LCMXO2280C-3FT256C VHDL clk_i > 50 MHz 33 23 LUTs 1.2
LFXP2-5E-5TN144C Verilog clk_i > 50 MHz 33 25 LUTs 1.2
LFXP2-5E-5TN144C VHDL clk_i > 50 MHz 33 25 LUTs 1.2

* May work in other devices as well.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.


Technical Resources
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WISHBONE-Compatible LCD Controller - Source Code
RD1053 1.2 11/8/2010 ZIP 140.9 KB
LCD Controller - Documentation
RD1149 1.0 4/9/2013 PDF 483.8 KB
LCD Controller - Source Code
RD1149 1.0 4/8/2013 ZIP 163 KB

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