SPI Slave IP Core

SPI Bus Interface

The Serial Peripheral Interface (SPI) is a high-speed synchronous, serial, full-duplex interface that allows a serial bit stream of configured length (8, 16, 24, and 32 bits) to be shifted into and out of the device at a programmed bit-transfer rate.

Features

  • Back-end LMMI Interface
  • Clock Polarity and Clock Phase modes – 00, 01, 10, 11
  • Configurable Serial Clock period
  • Configurable data width
  • Configurable Read and Write Data FIFO (8, 16, 24, or 32 bits wide)

Block Diagram

Ordering Information

Available for free to use in Lattice Radiant design software.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
SPI Slave IP Core - Lattice Radiant Software
FPGA-IPUG-02070 1.6 5/31/2022 PDF 936 KB
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