Avant-E

Optimized for Edge Processing Applications

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The Lattice Avant™-E family of mid-range FPGAs are the first products built using the 16nm FinFET Avant platform. This platform has been optimized to deliver the lowest power, smallest form factor, and highest performance FPGA devices in their class. The Avant-E family delivers the highest DSP and embedded memory to logic ratio for mid-range FPGAs, enabling intelligence at the edge for applications in automotive, communications, compute, and industrial market segments.

High Performance, Compact, and low power – High logic capacity from 262k to 637k System Logic Cells, smallest 11 x 9 mm package option, and up to 2.5x lower power than competition

Fast External Memory Support - LPDDR4/DDR4 at 1866 Mbps

Efficient Edge AI Processing – Up to 7200 INT8 multipliers and 36 Mb embedded memory enable more efficient implementation of AI/ML algorithms

Lattice will introduce additional Avant families to leverage the full capabilities of the platform. Click here to be notified as new devices become available.

Features

  • Up to 637k System Logic Cells, 36 Mb of embedded memory and 1800 - 18x18 multipliers (7200 - 8x8 multipliers)
  • Lowest power: Up to 2.5x lower power than competitive FPGAs in similar density
  • Packages as small as 11x9 mm (262k SLCs) or 15x13 mm (637k SLCs)
  • AI optimized DSP block enables 18x18 multipliers that can be split into four 8x8 multipliers
  • Fast configuration: I/O configures in 10ms, and full configuration for 637k SLCs in 60 ms
  • Available in Commercial and Industrial Grades

Jump to

Family Table

Avant-AT-E Family Selection Guide4
Features E30 E50 E70
System Logic Cells 262k
 409k
 637k
Look-Up-Tables (LUTs) 163k
 255k
 397k
Embedded Memory (EBR) Blocks (36 kb) 400 630 990
Embedded Memory (Mb) 14.4 22.7 35.6
Distributed RAM Bits (kb) 1700 2660 4140
DSP (18x18 Multipliers) 700 1120 1800
DSP (8x8 Multipliers)1 2800
 4480 7200
High Frequency Oscillator (400 MHz) 1 1 1
GPLL
 7
 9
 11
External Memory Interface support LPDDR4/DDR43 LPDDR4/DDR4 LPDDR4/DDR43
Temperature Grades2 C, I C, I C, I
0.5 mm Total I/O (Wide Range, High Performance)
  E30 E50 E70
ASG410 (9 x 11 mm) FOWLP
 247 (94,153) - -
CSG841 (15 x 15 mm) FCCSP
 - 553 (94, 459) 553 (94,459)
0.8 mm Total I/O (Wide Range, High Performance)
  E30 E50 E70
CBG484 (18 x 18 mm) FCCSP
 329 (94,235) 329 (94,235) 349 (94,255)
1.0 mm Total I/O (Wide Range, High Performance)
  E30 E50 E70
LFG676 (27 x 27 mm) FCBGA
 - - 297 (42,255)
LFG1156 (35 x 35 mm) FCBGA
 - - 553 (94,459)

1. One 18x18 multiplier fractures into four 8x8 multipliers
2. C=Commercial, I=Industrial
3. DDR4 is not supported in E70B or E30B variants
4. B variants only support limited package options. Refer to the datasheet’s Ordering Information for more details.

Example Use Cases

Industrial Networking / Gateway Block DiagramExpand Image

Industrial Switch / Gateway

  • Flexible Industrial Ethernet and Field Bus Interfaces
  • RISC-V CPU and Lattice Propel System Design Tools HW
  • Low Latency, deterministic switching and control processing, protocol acceleration
Machine Vision Block DiagramExpand Image

IP Network Camera

  • Sensor Interface - MIPI CSI-2, LVDS
  • Customizable ISP for image processing
  • Lattice sensAI Artificial Intelligence for object/defect detection
  • JPEG-XS compression enables lossless low latency streaming over Gigabit IP Networks
Robot Vision and Control Block DiagramExpand Image

Robot Vision and Control

  • Multi-channel Camera / sensor bridging and aggregation
  • Multi-channel Camera / sensor pre-processing and synchronization
  • Real time sync, sense & control, multi-axis
  • Internal Soft CPU and/or External CPU
Smart IP Network Camera Block DiagramExpand Image

Smart IP Network Camera

  • IP Network, GigE Vision output
  • MIPI CSI-2, LVDS sensor interface and control
  • Image Signal Processing
  • Computer Vision / AI / ML processing
  • Optional Lossless Compression – reduce BW 10X
  • Streaming over IP networks
Automotive Zonal Controller / Gateway Example Block Diagram - AvantExpand Image

Zonal Controller / Gateway for Centralized Compute Architectures

  • Ultra-low latency HW-optimized routing
  • Flexible Ethernet and sensor / actuator port configurations
  • Flexible video & image resolution and interface support
  • Optional low latency, lossless compression to optimize Camera transmission bandwidth requirements
  • Integrated state of the art HW accelerated security engine

Videos

Flying Ball Tracking & Catching
Expand Video

Flying Ball Tracking & Catching

In this demo, we present a robot equipped with advanced camera and radar technologies, designed to catch a ball thrown by a human. The system integrates real-time image and radar data processing to accurately track the ball’s trajectory and position. This demonstration highlights the robot’s precision and responsiveness, showcasing the potential for advanced robotics in dynamic and interactive environments.
MosChip Company Opensource RISC-V Core Running Zephyr RTOS on Various Lattice FPGAs
Expand Video

MosChip Company Opensource RISC-V Core Running Zephyr RTOS on Various Lattice FPGAs

This demonstration showcases the open-source Zephyr RTOS running on a RISC-V core with Lattice FPGA and various peripherals. By combining Zephyr and RISC-V, we create a reliable and flexible open-source embedded system. This approach leverages the community development ecosystem for faster time to market while maximizing customization features as needed.
Sensor Fusion - Radar, LiDAR, Camera + Robot Arm control
Expand Video

Sensor Fusion - Radar, Lidar, Camera + Robot Arm Control

This demo processes radar, LiDAR, and camera sensors simultaneously, showcasing the fused data processing among the sensors in real time. It demonstrates the flexibility of I/O and the computing power to handle multiple sensors and machine learning (ML). Sensor data (camera, radar, pressure) is pre-processed by the FPGA and sent to the CPU (Raspberry Pi) over PCIe. The CPU controls the robot arm and sends position info back to the FPGA, which generates commands for the arm.
Lattice Avant™ FPGA Platform: Power Efficiency Demo
Expand Video

Lattice Avant™ FPGA Platform: Power Efficiency Demo

Watch how the Lattice Avant FPGA platform delivers up to 2.5X lower power than similar class competitive devices, helping system and application engineers achieve power efficiency while simplifying thermal management and lowering operating costs.
Lattice Avant™ FPGA Platform: AI Processing Demo
Expand Video

Lattice Avant™ FPGA Platform: AI Processing Demo

Watch how the Lattice Avant FPGA platform provides scalable AI performance for Automotive applications. Lattice Avant FPGAs are designed to solve key customer challenges at the Edge by combining class-leading power efficiency, size and performance with an optimized feature set tailored to the needs of Edge applications like data processing and AI.

Design Resources

Development Kits & Boards

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Intellectual Property & Reference Designs

Simplify your design efforts by using pre-tested, reusable functions

Software

Complete Design Flows, High Ease of Use

Documentation

Quick Reference
Technical Resources
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
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[IBIS] Avant
FPGA-MD-02039 0.85 3/31/2025 ZIP 29.2 MB
[IBIS AMI] LAV-AT
This document would be provided through Technical Support Request after sign-in to the Lattice web site. Please refer to Answer Database FAQ 6539 for detailed instructions. 		FPGA-MD-02041 0.82 6/10/2024 WEB
Avant E/G/X Delphi Models (Preliminary)
FPGA-MD-02038 0.82 10/1/2024 ZIP 25.3 KB
Lattice Avant Platform - Specifications Data Sheet
FPGA-DS-02112 1.2 3/6/2025 PDF 1.9 MB
Lattice Avant-E70 Pinout
FPGA-SC-02037 0.89 3/6/2025 CSV 67.6 KB
Lattice Avant-E30 Pinout
FPGA-SC-02053 0.83 2/19/2025 CSV 42.6 KB
Triple-Speed Ethernet MAC Driver API Reference
FPGA-TN-02341 1.1 7/29/2024 PDF 398.2 KB
Lattice Avant SED/SEC User Guide
FPGA-TN-02290 0.81 10/24/2024 PDF 438.9 KB
Lattice Avant Multi-Boot User Guide
FPGA-TN-02314 0.84 12/15/2024 PDF 1.7 MB
Lattice Avant Hardware Checklist
FPGA-TN-02317 1.0 12/18/2024 PDF 1 MB
Lattice Avant sysCONFIG User Guide
FPGA-TN-02299 0.86 1/16/2025 PDF 3.3 MB
Lattice Avant sysCLOCK PLL Design and User Guide
FPGA-TN-02298 0.87 2/5/2025 PDF 1.1 MB
Lattice Avant sysI/O User Guide
FPGA-TN-02297 0.83 9/22/2024 PDF 691.3 KB
Lattice Avant sysDSP User Guide
FPGA-TN-02293 0.85 3/6/2025 PDF 795.4 KB
Lattice Avant SerDes/PCS User Guide
FPGA-TN-02313 0.84 9/29/2024 PDF 1.8 MB
Lattice Avant Power User Guide
FPGA-TN-02291 0.83 12/5/2023 PDF 439.4 KB
Lattice Avant High-Speed I/O and External Memory Interface User Guide
FPGA-TN-02300 1.0 10/8/2024 PDF 1.9 MB
Lattice Avant Embedded Memory User Guide
FPGA-TN-02289 0.82 9/24/2024 PDF 1.5 MB
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-02028 2.6 12/10/2024 PDF 560.4 KB
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 5.6 12/10/2024 PDF 6.2 MB
Thermal Management
FPGA-TN-02044 5.5 3/6/2025 PDF 771.6 KB
Minimizing System Interruption During Configuration Using TransFR Technology
FPGA-TN-02198 4.5 3/6/2025 PDF 1.6 MB
I3C Target Driver API Reference
FPGA-TN-02338 1.0 12/21/2023 PDF 769.7 KB
I3C Controller Driver API Reference
FPGA-TN-02342 1.0 12/21/2023 PDF 894.8 KB
Using TraceID
FPGA-TN-02084 2.8 4/15/2025 PDF 493.8 KB
Lattice Avant Platform - Overview Data Sheet
FPGA-DS-02107 1.3 5/13/2025 PDF 1 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Lattice Avant Platform - Specifications Data Sheet
FPGA-DS-02112 1.2 3/6/2025 PDF 1.9 MB
Lattice Avant Platform - Overview Data Sheet
FPGA-DS-02107 1.3 5/13/2025 PDF 1 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Triple-Speed Ethernet MAC Driver API Reference
FPGA-TN-02341 1.1 7/29/2024 PDF 398.2 KB
Migrating Designs from AMD CPLD/FPGA Devices to Lattice FPGA Devices
FPGA-AN-02081 1.1 8/27/2024 PDF 2.6 MB
Lattice Avant SED/SEC User Guide
FPGA-TN-02290 0.81 10/24/2024 PDF 438.9 KB
Lattice Avant Multi-Boot User Guide
FPGA-TN-02314 0.84 12/15/2024 PDF 1.7 MB
Lattice Avant Hardware Checklist
FPGA-TN-02317 1.0 12/18/2024 PDF 1 MB
Lattice Avant sysCONFIG User Guide
FPGA-TN-02299 0.86 1/16/2025 PDF 3.3 MB
Lattice Avant sysCLOCK PLL Design and User Guide
FPGA-TN-02298 0.87 2/5/2025 PDF 1.1 MB
Lattice Avant sysI/O User Guide
FPGA-TN-02297 0.83 9/22/2024 PDF 691.3 KB
Lattice Avant sysDSP User Guide
FPGA-TN-02293 0.85 3/6/2025 PDF 795.4 KB
Lattice Avant SerDes/PCS User Guide
FPGA-TN-02313 0.84 9/29/2024 PDF 1.8 MB
Lattice Avant Power User Guide
FPGA-TN-02291 0.83 12/5/2023 PDF 439.4 KB
Lattice Avant High-Speed I/O and External Memory Interface User Guide
FPGA-TN-02300 1.0 10/8/2024 PDF 1.9 MB
Lattice Avant Embedded Memory User Guide
FPGA-TN-02289 0.82 9/24/2024 PDF 1.5 MB
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-02028 2.6 12/10/2024 PDF 560.4 KB
Solder Reflow Guide for Surface Mount Devices
FPGA-TN-02041 5.0 12/10/2024 PDF 568.4 KB
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 5.6 12/10/2024 PDF 6.2 MB
Thermal Management
FPGA-TN-02044 5.5 3/6/2025 PDF 771.6 KB
Minimizing System Interruption During Configuration Using TransFR Technology
FPGA-TN-02198 4.5 3/6/2025 PDF 1.6 MB
I3C Target Driver API Reference
FPGA-TN-02338 1.0 12/21/2023 PDF 769.7 KB
I3C Controller Driver API Reference
FPGA-TN-02342 1.0 12/21/2023 PDF 894.8 KB
Using TraceID
FPGA-TN-02084 2.8 4/15/2025 PDF 493.8 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Avant Package Diagram
FPGA-DS-02123 1.1 2/25/2025 ZIP 377.1 KB
Lattice Avant-E70 Pinout
FPGA-SC-02037 0.89 3/6/2025 CSV 67.6 KB
Lattice Avant-E30 Pinout
FPGA-SC-02053 0.83 2/19/2025 CSV 42.6 KB
Lattice Avant-E70B Pinout
FPGA-SC-02055 1.0 3/30/2025 CSV 56.4 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Lattice OrCAD Capture Schematic Library (OLB)
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs. 		FPGA-SC-02005 8.4 12/10/2024 ZIP 2.7 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Product Selector Guide
I0211 48.0 12/10/2024 PDF 13.6 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Introducing the Lattice Avant™ Platform: Designed for the Mid-Range
1.0 12/5/2022 PDF 539.7 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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[BSDL] LAV-AT-500E LFG1156
FPGA-MD-02037 02A 8/15/2023 BSM 104.3 KB
[BSDL] LAV-AT-E30
FPGA-MD-02082 1.0 10/8/2024 ZIP 19.9 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Avant E/G/X Delphi Models (Preliminary)
FPGA-MD-02038 0.82 10/1/2024 ZIP 25.3 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
[IBIS] Avant
FPGA-MD-02039 0.85 3/31/2025 ZIP 29.2 MB
[IBIS AMI] LAV-AT
This document would be provided through Technical Support Request after sign-in to the Lattice web site. Please refer to Answer Database FAQ 6539 for detailed instructions. 		FPGA-MD-02041 0.82 6/10/2024 WEB

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