Power Manager II

Integrated board power management functions for the forward thinking engineer

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Power control, without the touch of a button – With Power Manager you can monitor and control up to 12 power supplies with unparalleled accuracy and speed, and respond to faults in <65 μs to protect on-board flash memory from corruption.

Reduce BOM costs– The easiest way to manage board-mounted power supplies – Power Manager II integrates hot-swap controllers, power supply OR’ing, sequencing, voltage monitoring, reset generation, trimming, margining, and more.

Design made simple – PAC-Designer software supports the Power Manager II family offering the convenience of design and verification of power sequencing and monitoring circuit using PC-based software – prior to uploading to the device.

Features

  • Up to 12 differential voltage sensors with immunity to noise on ground plane
  • Voltage trimming to within 1%
  • Ruggedized CPLD with up to 48 macrocells for sequencing and supervisory signal logic
  • Large operating power supply range (3.3 V + 20% to 3.3 V -15%)
  • Up to 4 High-Voltage MOSFET Driver Outputs
  • Voltage Measurement with 10-bit ADC through I2C
  • Up to 8 On-chip DACs for Margining and Trimming

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Family Table

Power Manager II Application Cross Reference Guide

  ProcessorPM POWR607 POWR1014 POWR1014A POWR1220AT8
Board input (Primary) Supply Management Hot-swap
-48V Hot-swap   Check Mark Check Mark Check Mark Check Mark
+12/24V Hot Swap   Check Mark Check Mark Check Mark Check Mark
Power Feed To External Systems
-48V Supply Feed   Check Mark Check Mark Check Mark Check Mark
+12/24V Supply Feed   Check Mark Check Mark Check Mark Check Mark
Redundant Supply Selection
-48V Supply O R'ing   Check Mark Check Mark Check Mark Check Mark
+12/24V Supply O R'ing   Check Mark Check Mark Check Mark Check Mark
Payload (Secondary) Power Management
Supply Sequencing   Check Mark Check Mark Check Mark Check Mark
Voltage Supervision Check Mark Check Mark Check Mark Check Mark Check Mark
Reset Generation Check Mark Check Mark Check Mark Check Mark Check Mark
Watchdog Timer Check Mark Check Mark Check Mark Check Mark Check Mark
Voltage Measurement Using ADC       Check Mark Check Mark
Power Supply Voltage Trimming         Check Mark
Power Supply Margining         Check Mark

Lattice Automotive (AEC-Q100 qualified) ispPAC-POWR1014/A Device Selection Guide

  LA-POWR1014 LA-POWR1014A
Analog Input Pins 10 10
Programmable Comparators 20 20
Trip Point per input 368 368
Lowest Supply Voltage Monitored 0.7V 0.7V
Power-off Detection 75mV 75mV
CPLD Macrocells 24 24
Outputs 14 14
FET Drivers 2 2
ADC Resolution - 10 Bits
I2C Support - Yes
Operating Voltage 2.8V to 3.9V 2.8V to 3.9V
Package 48-Pin TQFP 48-Pin TQFP

Example Solutions

Avoid flash corruption by accurately monitoring up to 12 rails for faults

  • High precision analog fault detection circuitry is integrated with digital control logic (a PLD) in a single-chip
  • Monitor up to 12 rails for faults accurately, quickly issue flags and control board operation.
  • Prevent flash corruption by accurately monitoring all processor power supply rails. Respond to faults with a processor reset in under 16µs.

Save development time and effort by reusing a single-chip, scalable power management solution.

  • Enables scalability as the system bandwidth and power requirements grow from 4 to 12 rails in one chip.
  • Fine tune power supply sequencing without board modifications to enable reliable board start-up
  • Simulate the effects of different fault conditions using simple point-and-click software

Reduce system cost by implementing reliable hot-swap using lowest cost MOSFETs

  • Implement reliable, high-power hot-swap controller without using expensive big MOSFETs
  • Reduce the total number of MOSFETs required – and use smaller low-cost, conventional MOSFETs

Reduce cost by 50% through integration of reset generator, voltage monitor, and watchdog timer into a single Power Manager device.

  • Replace numerous single function ICs and discretes with one Power Manager device – significantly reducing board-space and cost.

Accurately adjust for brown-outs by quickly switching to back-up power in less than 16µs

  • Maintain power to small cells during brown-out
  • Ride through brown-out periods by automatically switching to a back up through fast, accurate voltage monitoring.

Design Resources

Intellectual Property & Reference Designs

Simplify your design efforts by using pre-tested, reusable functions

Application Notes

Learn how to get the most from our line-up of FPGAs / development boards

Software

Complete Design Flows, High Ease of Use

Development Kits & Boards

Our development boards & kits help streamline your design process

Programming Hardware

Take the strain out of in-system programming & in-circuit reconfiguration with our programming hardware

Documentation

Quick Reference
Technical Resources
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
High-side Current Sensing Techniques for Power Manager Devices
AN6049 01.1 4/17/2008 PDF 70.9 KB
Extending the VMON Input Range of Power/Platform Management Devices
FPGA-AN-02031 2.5 9/21/2021 PDF 1.1 MB
Fail-Safe Sequencing During Field Upgrades Source Files
DT6088 1.2 6/6/2012 ZIP 591.5 KB
Fail-Safe Sequencing During Field Upgrades with Platform Manager
AN6088 01.2 6/6/2012 PDF 1.1 MB
Monitoring and Controlling Negative Power Supplies with Power Manager Devices
AN6051 02.1 4/17/2008 PDF 67.9 KB
Optimizing the Accuracy of ispPAC Power Manager Timers
AN6076 01.0 12/12/2007 PDF 215.9 KB
ispPAC-POWR1220AT8 Evaluation Board
AN6065 01.2 3/1/2007 PDF 305.3 KB
Interfacing the Trim Output of Power Manager II Devices to DC-DC Converters
AN6074 1.2 4/7/2015 PDF 3.1 MB
ispPAC-POWR1220AT8 I2C Hardware Verification Utility
AN6067 01.0 11/21/2005 PDF 563.7 KB
Interfacing Power Manager Devices with Modular DC-to-DC Converters
AN6046 01.1 4/17/2008 PDF 494.6 KB
Implementing Power Supply Sequencers with Power/Platform Management Devices and PAC-Designer LogiBuilder
AN6042 01.2 10/7/2011 PDF 277 KB
ispPAC-POWR1014/A Data Sheet
FPGA-DS-02089 2.3 11/20/2020 PDF 4.7 MB
Using the HVOUT Simulator Utility to Estimate FET Ramp Times
AN6070 01.0 11/21/2005 PDF 540.1 KB
Using Power MOSFETs with Power/Platform Management Devices
AN6048 1.3 8/29/2017 PDF 734.6 KB
Using ispVM System to Program ispPAC Devices
AN6062 01.0 5/1/2004 PDF 709.2 KB
Using PAC-Designer's Power Manager Waveform Editor
AN6054 01.0 11/23/2005 PDF 276.3 KB
Controlling and Monitoring Power-One Bricks and SIPs with Lattice Power Manager Devices
AN6056 01.1 4/17/2008 PDF 216.1 KB
Powering Up and Programming the ProcessorPM ispPAC-POWR605
AN6082 01.1 4/21/2011 PDF 1.1 MB
Simulating Power Supply Sequences for Power Manager Devices Using PAC-Designer LogiBuilder
AN6044 1.1 4/17/2008 PDF 409.4 KB
Programming the ispPAC-POWR1220AT8 in a JTAG Chain Using the ATDI Pin
AN6068 01.1 2/28/2011 PDF 245.8 KB
Powering Up and Programming the ispPAC-POWR1220AT8
AN6073 01.1 4/21/2011 PDF 171.2 KB
Powering Up and Programming the ispPAC-POWR607
AN6078 01.1 4/21/2011 PDF 1.3 MB
Programmable Comparator Options for ispPAC-POWR1220AT8
AN6069 01.0 11/21/2005 PDF 259.4 KB
Scalable Centralized Power Management Source Files
DT6089 1.2 6/6/2012 ZIP 520.7 KB
Scalable Centralized Power Management with Field Upgrade Support
AN6089 01.2 6/6/2012 PDF 1.1 MB
Stable Operation of DC-DC Converters with Power Manager Closed Loop Trim
AN6077 1.1 10/8/2014 PDF 676.8 KB
Powering Up and Programming the ispPAC-POWR1014/A
AN6075 01.1 4/11/2011 PDF 190.4 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
ProcessorPM - POWR605 Data Sheet
DS1034 2.0 4/10/2015 PDF 2.7 MB
ispPAC-POWR607 Data Sheet
DS1011 2.0 4/27/2015 PDF 2.7 MB
ispPAC-POWR1220AT8 Data Sheet
FPGA-DS-02051 2.0 4/11/2019 PDF 4.9 MB
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
FPGA-DS-02090 1.4 10/26/2020 PDF 5.6 MB
ispPAC-POWR1014/A Data Sheet
FPGA-DS-02089 2.3 11/20/2020 PDF 4.7 MB
ispPAC-POWR6AT6 Data Sheet
DS1016 1.5 11/13/2013 PDF 3.2 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
High-side Current Sensing Techniques for Power Manager Devices
AN6049 01.1 4/17/2008 PDF 70.9 KB
Extending the VMON Input Range of Power/Platform Management Devices
FPGA-AN-02031 2.5 9/21/2021 PDF 1.1 MB
Fail-Safe Sequencing During Field Upgrades Source Files
DT6088 1.2 6/6/2012 ZIP 591.5 KB
Fail-Safe Sequencing During Field Upgrades with Platform Manager
AN6088 01.2 6/6/2012 PDF 1.1 MB
Monitoring and Controlling Negative Power Supplies with Power Manager Devices
AN6051 02.1 4/17/2008 PDF 67.9 KB
Optimizing the Accuracy of ispPAC Power Manager Timers
AN6076 01.0 12/12/2007 PDF 215.9 KB
ispPAC-POWR1220AT8 Evaluation Board
AN6065 01.2 3/1/2007 PDF 305.3 KB
Interfacing the Trim Output of Power Manager II Devices to DC-DC Converters
AN6074 1.2 4/7/2015 PDF 3.1 MB
ispPAC-POWR1220AT8 I2C Hardware Verification Utility
AN6067 01.0 11/21/2005 PDF 563.7 KB
Interfacing Power Manager Devices with Modular DC-to-DC Converters
AN6046 01.1 4/17/2008 PDF 494.6 KB
Implementing Power Supply Sequencers with Power/Platform Management Devices and PAC-Designer LogiBuilder
AN6042 01.2 10/7/2011 PDF 277 KB
Using the HVOUT Simulator Utility to Estimate FET Ramp Times
AN6070 01.0 11/21/2005 PDF 540.1 KB
Using Power MOSFETs with Power/Platform Management Devices
AN6048 1.3 8/29/2017 PDF 734.6 KB
Using ispVM System to Program ispPAC Devices
AN6062 01.0 5/1/2004 PDF 709.2 KB
Using PAC-Designer's Power Manager Waveform Editor
AN6054 01.0 11/23/2005 PDF 276.3 KB
Using the ABEL Tools of PAC-Designer with Power Manager Devices
AN6052 02.0 5/1/2003 PDF 777 KB
Controlling and Monitoring Power-One Bricks and SIPs with Lattice Power Manager Devices
AN6056 01.1 4/17/2008 PDF 216.1 KB
Powering Up and Programming the ProcessorPM ispPAC-POWR605
AN6082 01.1 4/21/2011 PDF 1.1 MB
Simulating Power Supply Sequences for Power Manager Devices Using PAC-Designer LogiBuilder
AN6044 1.1 4/17/2008 PDF 409.4 KB
Programming the ispPAC-POWR1220AT8 in a JTAG Chain Using the ATDI Pin
AN6068 01.1 2/28/2011 PDF 245.8 KB
Powering Up and Programming the ispPAC-POWR1220AT8
AN6073 01.1 4/21/2011 PDF 171.2 KB
Powering Up and Programming the ispPAC-POWR607
AN6078 01.1 4/21/2011 PDF 1.3 MB
Programmable Comparator Options for ispPAC-POWR1220AT8
AN6069 01.0 11/21/2005 PDF 259.4 KB
Scalable Centralized Power Management Source Files
DT6089 1.2 6/6/2012 ZIP 520.7 KB
Scalable Centralized Power Management with Field Upgrade Support
AN6089 01.2 6/6/2012 PDF 1.1 MB
Stable Operation of DC-DC Converters with Power Manager Closed Loop Trim
AN6077 1.1 10/8/2014 PDF 676.8 KB
Powering Up and Programming the ispPAC-POWR1014/A
AN6075 01.1 4/11/2011 PDF 190.4 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
ispPAC-POWR607 Evaluation Board User's Guide
Describes the features and functions of the ispPAC-POWR607 Evaluation Board 		5/23/2007 PDF 1.2 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Voltage Monitoring for Fault Logging - Documentation
RD1072 1.0 4/26/2010 PDF 447.5 KB
Voltage Monitoring for Fault Logging - Source Code
RD1072 1.0 4/26/2010 ZIP 327.3 KB
Supervisor, WDT and Reset Generation with ProcessorPM - Source Code
RD1056 1.0 8/3/2009 ZIP 744.4 KB
Supervisor, WDT and Reset Generation with ProcessorPM - Documentation
RD1056 1.0 8/17/2009 PDF 815.7 KB
Hercules Development Kit Demonstration Source Code
1.0 6/11/2010 ZIP 201.6 KB
12V Hot Swap Control - Documentation
RD1068 1.0 4/26/2010 PDF 469.8 KB
AMC Module Power Management - Documentation
RD1070 1.0 4/26/2010 PDF 532.3 KB
AMC Module Power Management - Source Code
RD1070 1.0 4/26/2010 ZIP 468.3 KB
5V and 3.3V Hot Swap Controller - Source Code
RD1057 1.0 8/6/2009 ZIP 135 KB
5V and 3.3V Hot Swap Controller - Documentation
RD1057 1.0 8/4/2009 PDF 185.3 KB
12V Hot Swap Control - Source Code
RD1068 1.0 4/26/2010 ZIP 371.1 KB
Redundant Power Supply Management
RD1064 1.0 4/26/2010 PDF 508.9 KB
Redundant Power Supply Management - Source Code
RD1064 1.0 4/26/2010 ZIP 441.3 KB
OrCAD Capture (.dsn) format schematics
1 9/28/2010 ZIP 0.7 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
PCN07B-19 Unisem Shutdown
PCN07B-19 11/26/2019 PDF 348.2 KB
PCN13A-10 Notification of intent to discontinue select mature devices
PCN13A-10 1 9/7/2010 PDF 163.7 KB
PCN13A-10 Notification of intent to discontinue select mature devices - Japanese Language
PCN13A-10 1 9/7/2010 PDF 205.1 KB
PCN06C-11 Withdrawal of PCN06B-11
Material Set 		PCN06C-11 1.0 8/1/2011 PDF 838.5 KB
ACN03D-11 Withdrawal of ACN03C-11
Material Set 		ANC03D-11 1 4/1/2011 PDF 796.6 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Lattice OrCAD Capture Schematic Library (OLB)
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs. 		FPGA-SC-02005 8.2 8/8/2024 ZIP 2.6 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Power Failure Protection for Solid State Drives
Illustrates several power management improvements for SSD that improve reliablity while lowering system costs. 		I0227 1.0 6/7/2012 PDF 864.3 KB
ProcessorPM Development Kit Product Brief
I0202 1.0 5/22/2013 PDF 673.4 KB
ProcessorPM - POWR605 Product Brochure
I0201 1.0 4/24/2009 PDF 1.6 MB
Power Manager II Product Brief (Chinese)
I0178C 6.0 11/13/2012 PDF 2.1 MB
Power Manager II Product Brief
I0178 7.0 8/14/2013 PDF 1.7 MB
Power Manager II and ispClock Application Examples
I0191 2.0 8/1/2007 PDF 456.1 KB
Automotive Solutions Product Brief
I0164 8.0 6/5/2009 PDF 2.4 MB
Product Selector Guide
I0211 46.0 7/18/2024 PDF 9.7 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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TN_VN100_4k_M4A_PAC
Rev B1 10/13/2021 PDF 124.1 KB
SN_SG32
Rev I 5/1/2024 PDF 145.6 KB
TN_VN48 (PAC, M4A)
Rev B 2/7/2018 PDF 25.3 KB
SN24_PAC
Rev F 2/7/2018 PDF 22.1 KB
32 QFNS Pb-Free Device Material Content
Includes all 3 versions 		D 4/19/2016 PDF 51.1 KB
Lattice ispPAC-POWR Product Family Qualification Summary
J 1/22/2021 PDF 493 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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PAC-Designer Tutorial: Designing Power Manager II
This tutorial shows you how to use several processes, tools, and reports of the PAC-Designer software suite to program digital and analog elements of the ispPAC®-POWR1220AT8 device. 		PDT01 01.1 8/15/2008 PDF 1.3 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Distributed PLD Solution for Reduced Server Cost and Increases Flexibility
WP009 1.0 8/1/2017 PDF 708.1 KB
Complex Power Management: An Imperative for Modern System Design
11/1/2005 PDF 220.6 KB
Dynamic Power Management in an Embedded System
4/1/2005 PDF 619.6 KB
Reset Generation for TI DSP Processor (Chinese Language)
1.0 6/28/2010 PDF 226.5 KB
Transforming Circuit Board Design (Chinese Language)
1.0 9/26/2011 PDF 449.1 KB
Reset Generation for TI DSP Processor (Traditional Chinese Language)
1.0 6/28/2010 PDF 286 KB
Power Management for Computer Peripherals - White Paper (Chinese Language Version)
1.0 5/31/2012 PDF 262.8 KB
Reset Generation for TI DSP Processor
1.0 3/1/2010 PDF 64.9 KB
Reset Generation for TI DSP Processor (Japanese Language)
1.0 3/1/2010 PDF 156.6 KB
Transforming Circuit Board Design
1.0 9/26/2011 PDF 424.3 KB
Reset Generation for TI DSP Processor (Korean Language)
1/1/0001 PDF 321.1 KB
Load Switching Helps Implement Hot Swaping
1.0 3/1/2010 PDF 215.9 KB
Managing Power Sequencing for the LatticeSC FPGA
2/1/2007 PDF 312.9 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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[BSDL] ispPAC-POWR1014 48-pin TQFP
1.00 4/11/2006 BSM 8.2 KB
[BSDL] ispPAC-POWR607 24-pin QFN
1.0 8/1/2014 BSM 7.4 KB
[BSDL] ispPAC-POWR605 24-pin QFNS
1.0 4/27/2009 BSM 8.1 KB
[BSDL] ispPAC-POWR1014A 48-pin TQFP
1.00 4/1/2006 BSM 7.8 KB
[BSDL] ispPAC-POWR6AT6 32-pin QFN
1.0 2/1/2007 BSM 7.9 KB
[BSDL] ispPAC-POWR607 32-pin QFN
1.0 2/1/2007 BSM 7.5 KB
[BSDL] ispPAC-POWR1220AT8 100-pin TQFP
1.02 5/24/2006 BSM 12.9 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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[IBIS] ispPAC-POWR605
0.1 7/1/2009 IBS 174.8 KB
[IBIS] ispPAC-POWR1014/1014A
0.1 2/1/2007 IBS 276.6 KB
[IBIS] ispPAC-POWR607
0.1 2/1/2007 IBS 224.6 KB
[IBIS] ispPAC-POWR1220AT8
0.2 3/2/2012 IBS 412.3 KB
[IBIS] ispPAC-POWR6AT6
0.1 2/1/2007 IBS 145.2 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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POWR1014A Breakout Board Demo Source
This demo includes the PAC-Designer project source for the preprogrammed demonstration design. It programs the POWR1014A with power supply enable sequence logic and a counter circuit using the embedded timer & open-drain digital pins configured for LED 		1.0 3/21/2011 ZIP 7.4 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Selecting Power and Platform Manager Devices Excel Spreadsheet Tool
1.1 3/19/2012 ZIP 63.1 KB

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