パワーマネージャー2

先を見据えたエンジニアのための統合ボードパワー管理機能

ボタンの操作なしでの電力制御 - パワーマネージャーを使用すると、比類のない正確さと速度で最大12の電源をモニターおよび制御し、内蔵フラッシュメモリを破損から保護するために<65μsの障害に応答することができます。

BOMコストを最大50%削減 - 基板実装の電源を管理する最も簡単な方法 - パワーマネージャー2は、ホットスワップコントローラ、電源OR、シーケンシング、電圧監視、リセット生成、トリミング、マージニングなどを統合しています。

設計が簡単 - PACデザイナーソフトウェアは、パワーマネージャー2ファミリに対応しており、デバイスにアップロードする前に、PCベースのソフトウェアを使用して電源シーケンシングとモニタ回路の設計と検証の利便性を提供します。

特長

  • グランドプレーンのノイズ耐性を備えた最大12個の差動電圧センサー
  • 電圧トリミングを1%以内に
  • シーケンシングおよび監視信号ロジック用に最大48個のマクロセルを備えた堅牢なCPLD
  • 広範な動作電源レンジ(3.3 V + 20%から3.3 V -15%)
  • 最大4つの高電圧MOSFETドライバ出力
  • I2Cを経由した10ビットADCの電圧測定
  • マージニングおよびトリミング用の最大8個のオンチップDAC

リンクに飛ぶ

ファミリーテーブル

アプリケーション相互リファレンスガイド

  ProcessorPM POWR607 POWR1014 POWR1014A POWR1220AT8
ボード入力(一次側)電源管理
活線挿抜
-48V 活線挿抜   Check Mark      
+12/24V 活線挿抜   Check Mark Check Mark Check Mark Check Mark
外部システムへの給電
-48V 給電   Check Mark      
+12/24V 給電   Check Mark Check Mark Check Mark Check Mark
冗長電源切り替え制御
-48V 電源切り替え   Check Mark      
+12/24V 電源切り替え   Check Mark Check Mark Check Mark Check Mark
ペイロード(二次側)電源管理
電源シーケンス制御   Check Mark Check Mark Check Mark Check Mark
電圧監視 Check Mark Check Mark Check Mark Check Mark Check Mark
リセット生成 Check Mark Check Mark Check Mark Check Mark Check Mark
ウォッチドッグ・タイマ Check Mark Check Mark Check Mark Check Mark Check Mark
ADC を用いた電圧測定       Check Mark Check Mark
電源電圧のトリミング         Check Mark
電源電圧のマージン検証         Check Mark

ソリューション

ラティスのパワーマネージャ・ファミリは、複数のボードレベルの電源とデジタル管理機能を統合する、柔軟なプログラマブル・ソリューションを提供します。

最大12系統の故障を正確にモニタし、フラッシュメモリの意図せぬ書き換えを防止

  • 単一チップ内に、高精度アナログ故障検出回路とデジタル制御ロジック(PLD)を集積
  • 最大12系統の故障を正確に監視し、素早く通知してボードの動作を制御
  • プロセッサの全ての供給電源を正確に監視し、16µs未満での故障に対する反応でプロセッサをリセットし、フラッシュメモリの意図せぬ書き換えを防止

シングルチップでスケーラブルな電源管理ソリューションの再利用により、開発期間と労力を削減

  • ワンチップでシステム帯域幅と電源要件が4系統から12系統までスケーラブルに対応可能
  • 高い信頼性でボードを起動するために、ボードを改版せずに電源のシーケンス制御を微調整
  • シンプルなポイントアンドクリック・ソフトウェアを使用して、様々な故障状態による影響をシミュレート

信頼性の高い活線挿抜を実装することで、最低コストのMOSFETを使用してシステムコストを低減

  • 高価なMOSFETを使用することなく、信頼性の高い大電力活線挿抜コントローラを実装可能
  • 必要なMOSFETの総数を減少し、かつ小型で低コストの一般的なMOSFETを使用可能

リセット生成器と電圧モニタ、およびウォッチドッグタイマを単一電源管理デバイスに集積することで、コストを50%削減

  • 多数の単機能ICと個別部品をパワーマネージャで置換することで、ボードの面積とコストを大幅に削減可能

電圧低下時にバックアップ電源へ16µs以内に素早く切り替える正確な調整

  • 電圧低下時でもスモールセルへの電源を維持
  • 高速で正確な電圧モニタリングにより、電圧低下時でも自動的にバックアップに切り替え

デザインリソース

IP&リファレンスデザイン

プレテスト、再利用可能な機能を利用して設計の労力を軽減

アプリケーションノート


当社のFPGA、開発ボードのラインナップを最大活用する方法

ソフトウェア

使いやすい設計フローの完全版

開発キット&ボード

当社の開発キットとボードで設計プロセスの合理化

プログラミング ハードウェア

当社のプログラミングハードウェアでインシステム・プログラミング、インサーキット再構成の負担を軽減

ドキュメント

Quick Reference
Technical Resources
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
High-side Current Sensing Techniques for Power Manager Devices
AN6049 01.1 4/17/2008
Extending the VMON Input Range of Power/Platform Management Devices
AN6041 2.4 3/1/2016
Fail-Safe Sequencing During Field Upgrades Source Files
DT6088 1.2 6/6/2012
Fail-Safe Sequencing During Field Upgrades with Platform Manager
AN6088 01.2 6/6/2012
Monitoring and Controlling Negative Power Supplies with Power Manager Devices
AN6051 02.1 4/17/2008
Optimizing the Accuracy of ispPAC Power Manager Timers
AN6076 01.0 12/12/2007
ispPAC-POWR1220AT8 Evaluation Board
AN6065 01.2 3/1/2007
Interfacing the Trim Output of Power Manager II Devices to DC-DC Converters
AN6074 1.2 4/7/2015
ispPAC-POWR1220AT8 I2C Hardware Verification Utility
AN6067 01.0 11/21/2005
Interfacing Power Manager Devices with Modular DC-to-DC Converters
AN6046 01.1 4/17/2008
Implementing Power Supply Sequencers with Power/Platform Management Devices and PAC-Designer LogiBuilder
AN6042 01.2 10/7/2011
Using the HVOUT Simulator Utility to Estimate FET Ramp Times
AN6070 01.0 11/21/2005
Using Power MOSFETs with Power/Platform Management Devices
AN6048 1.3 8/29/2017
Using ispVM System to Program ispPAC Devices
AN6062 01.0 5/1/2004
Using PAC-Designer's Power Manager Waveform Editor
AN6054 01.0 11/23/2005
Powering Up and Programming the ProcessorPM ispPAC-POWR605
AN6082 01.1 4/21/2011
Simulating Power Supply Sequences for Power Manager Devices Using PAC-Designer LogiBuilder
AN6044 1.1 4/17/2008
Programming the ispPAC-POWR1220AT8 in a JTAG Chain Using the ATDI Pin
AN6068 01.1 2/28/2011
Powering Up and Programming the ispPAC-POWR1220AT8
AN6073 01.1 4/21/2011
Powering Up and Programming the ispPAC-POWR607
AN6078 01.1 4/21/2011
Programmable Comparator Options for ispPAC-POWR1220AT8
AN6069 01.0 11/21/2005
Scalable Centralized Power Management Source Files
DT6089 1.2 6/6/2012
Scalable Centralized Power Management with Field Upgrade Support
AN6089 01.2 6/6/2012
Powering Up and Programming the ispPAC-POWR1014/A
AN6075 01.1 4/11/2011
Stable Operation of DC-DC Converters with Power Manager Closed Loop Trim
AN6077 1.1 10/8/2014
Controlling and Monitoring Power-One Bricks and SIPs with Lattice Power Manager Devices
AN6056 01.1 4/17/2008
TITLE NUMBER VERSION DATE FORMAT SIZE
ispPAC-POWR607 Data Sheet
DS1011 2.0 4/27/2015
ispPAC-POWR1220AT8 Data Sheet
FPGA-DS-02051 2.0 4/11/2019
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
DS1018 1.3 9/26/2013
ispPAC-POWR1014/A Data Sheet
DS1014 2.2 11/2/2015
ispPAC-POWR6AT6 Data Sheet
DS1016 1.5 11/13/2013
ProcessorPM - POWR605 Data Sheet
DS1034 2.0 4/10/2015
TITLE NUMBER VERSION DATE FORMAT SIZE
High-side Current Sensing Techniques for Power Manager Devices
AN6049 01.1 4/17/2008
Extending the VMON Input Range of Power/Platform Management Devices
AN6041 2.4 3/1/2016
Fail-Safe Sequencing During Field Upgrades Source Files
DT6088 1.2 6/6/2012
Fail-Safe Sequencing During Field Upgrades with Platform Manager
AN6088 01.2 6/6/2012
Monitoring and Controlling Negative Power Supplies with Power Manager Devices
AN6051 02.1 4/17/2008
Optimizing the Accuracy of ispPAC Power Manager Timers
AN6076 01.0 12/12/2007
ispPAC-POWR1220AT8 Evaluation Board
AN6065 01.2 3/1/2007
Interfacing the Trim Output of Power Manager II Devices to DC-DC Converters
AN6074 1.2 4/7/2015
ispPAC-POWR1220AT8 I2C Hardware Verification Utility
AN6067 01.0 11/21/2005
Interfacing Power Manager Devices with Modular DC-to-DC Converters
AN6046 01.1 4/17/2008
Implementing Power Supply Sequencers with Power/Platform Management Devices and PAC-Designer LogiBuilder
AN6042 01.2 10/7/2011
Using the HVOUT Simulator Utility to Estimate FET Ramp Times
AN6070 01.0 11/21/2005
Using Power MOSFETs with Power/Platform Management Devices
AN6048 1.3 8/29/2017
Using ispVM System to Program ispPAC Devices
AN6062 01.0 5/1/2004
Using PAC-Designer's Power Manager Waveform Editor
AN6054 01.0 11/23/2005
Using the ABEL Tools of PAC-Designer with Power Manager Devices
AN6052 02.0 5/1/2003
Powering Up and Programming the ProcessorPM ispPAC-POWR605
AN6082 01.1 4/21/2011
Simulating Power Supply Sequences for Power Manager Devices Using PAC-Designer LogiBuilder
AN6044 1.1 4/17/2008
Programming the ispPAC-POWR1220AT8 in a JTAG Chain Using the ATDI Pin
AN6068 01.1 2/28/2011
Powering Up and Programming the ispPAC-POWR1220AT8
AN6073 01.1 4/21/2011
Powering Up and Programming the ispPAC-POWR607
AN6078 01.1 4/21/2011
Programmable Comparator Options for ispPAC-POWR1220AT8
AN6069 01.0 11/21/2005
Scalable Centralized Power Management Source Files
DT6089 1.2 6/6/2012
Scalable Centralized Power Management with Field Upgrade Support
AN6089 01.2 6/6/2012
Powering Up and Programming the ispPAC-POWR1014/A
AN6075 01.1 4/11/2011
Stable Operation of DC-DC Converters with Power Manager Closed Loop Trim
AN6077 1.1 10/8/2014
Controlling and Monitoring Power-One Bricks and SIPs with Lattice Power Manager Devices
AN6056 01.1 4/17/2008
TITLE NUMBER VERSION DATE FORMAT SIZE
ispPAC-POWR607 Evaluation Board User's Guide
Describes the features and functions of the ispPAC-POWR607 Evaluation Board
5/23/2007
TITLE NUMBER VERSION DATE FORMAT SIZE
Voltage Monitoring for Fault Logging - Source Code
RD1072 1.0 4/26/2010
Supervisor, WDT and Reset Generation with ProcessorPM - Source Code
RD1056 1.0 8/3/2009
Supervisor, WDT and Reset Generation with ProcessorPM - Documentation
RD1056 1.0 8/17/2009
Hercules Development Kit Demonstration Source Code
1.0 6/11/2010
12V Hot Swap Control - Documentation
RD1068 1.0 4/26/2010
AMC Module Power Management - Documentation
RD1070 1.0 4/26/2010
AMC Module Power Management - Source Code
RD1070 1.0 4/26/2010
5V and 3.3V Hot Swap Controller - Source Code
RD1057 1.0 8/6/2009
5V and 3.3V Hot Swap Controller - Documentation
RD1057 1.0 8/4/2009
12V Hot Swap Control - Source Code
RD1068 1.0 4/26/2010
Redundant Power Supply Management
RD1064 1.0 4/26/2010
Redundant Power Supply Management - Source Code
RD1064 1.0 4/26/2010
OrCAD Capture (.dsn) format schematics
1 9/28/2010
Voltage Monitoring for Fault Logging - Documentation
RD1072 1.0 4/26/2010
TITLE NUMBER VERSION DATE FORMAT SIZE
PCN07B-19 Unisem Shutdown
PCN07B-19 11/26/2019
PCN06C-11 Withdrawal of PCN06B-11
Material Set
PCN06C-11 1.0 8/1/2011
ACN03D-11 Withdrawal of ACN03C-11
Material Set
ANC03D-11 1 4/1/2011
PCN13A-10 Notification of intent to discontinue select mature devices
PCN13A-10 1 9/7/2010
PCN13A-10 Notification of intent to discontinue select mature devices - Japanese Language
PCN13A-10 1 9/7/2010
TITLE NUMBER VERSION DATE FORMAT SIZE
Lattice OrCAD Capture Schematic Library (OLB)
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
6.8 7/16/2020
TITLE NUMBER VERSION DATE FORMAT SIZE
Power Failure Protection for Solid State Drives
Illustrates several power management improvements for SSD that improve reliablity while lowering system costs.
I0227 1.0 6/7/2012
ProcessorPM Development Kit Product Brief
I0202 1.0 5/22/2013
ProcessorPM - POWR605 Product Brochure
I0201 1.0 4/24/2009
Power Manager II Product Brief (Chinese)
I0178C 6.0 11/13/2012
Power Manager II Product Brief
I0178 7.0 8/14/2013
Power Manager II and ispClock Application Examples
I0191 2.0 8/1/2007
Automotive Solutions Product Brief
I0164 8.0 6/5/2009
Product Selector Guide
I0211 26.0 7/9/2020
TITLE NUMBER VERSION DATE FORMAT SIZE
Lattice ispPAC-POWR Product Family Qualification Summary
H 3/1/2013
TN_VN100_4k_M4A_PAC
Rev B1 3/18/2020
SN_SG32
Rev G 12/20/2019
TN_VN48 (PAC, M4A)
Rev B 2/7/2018
SN24_PAC
Rev F 2/7/2018
32 QFNS Pb-Free Device Material Content
Includes all 3 versions
D 4/19/2016
TITLE NUMBER VERSION DATE FORMAT SIZE
PAC-Designer Tutorial: Designing Power Manager II
This tutorial shows you how to use several processes, tools, and reports of the PAC-Designer software suite to program digital and analog elements of the ispPAC®-POWR1220AT8 device.
PDT01 01.1 8/15/2008
TITLE NUMBER VERSION DATE FORMAT SIZE
Complex Power Management: An Imperative for Modern System Design
11/1/2005
Distributed PLD Solution for Reduced Server Cost and Increases Flexibility
WP009 1.0 8/1/2017
Dynamic Power Management in an Embedded System
4/1/2005
Reset Generation for TI DSP Processor (Chinese Language)
1.0 6/28/2010
Transforming Circuit Board Design (Chinese Language)
1.0 9/26/2011
Reset Generation for TI DSP Processor (Traditional Chinese Language)
1.0 6/28/2010
Power Management for Computer Peripherals - White Paper (Chinese Language Version)
1.0 5/31/2012
Reset Generation for TI DSP Processor
1.0 3/1/2010
Reset Generation for TI DSP Processor (Japanese Language)
1.0 3/1/2010
Transforming Circuit Board Design
1.0 9/26/2011
Reset Generation for TI DSP Processor (Korean Language)
1/1/0001
Load Switching Helps Implement Hot Swaping
1.0 3/1/2010
Managing Power Sequencing for the LatticeSC FPGA
2/1/2007
TITLE NUMBER VERSION DATE FORMAT SIZE
[BSDL] ispPAC-POWR1014 48-pin TQFP
1.00 4/11/2006
[BSDL] ispPAC-POWR607 24-pin QFN
1.0 8/1/2014
[BSDL] ispPAC-POWR605 24-pin QFNS
1.0 4/27/2009
[BSDL] ispPAC-POWR1014A 48-pin TQFP
1.00 4/1/2006
[BSDL] ispPAC-POWR6AT6 32-pin QFN
1.0 2/1/2007
[BSDL] ispPAC-POWR607 32-pin QFN
1.0 2/1/2007
[BSDL] ispPAC-POWR1220AT8 100-pin TQFP
1.02 5/24/2006
TITLE NUMBER VERSION DATE FORMAT SIZE
[IBIS] ispPAC-POWR605
0.1 7/1/2009
[IBIS] ispPAC-POWR1014/1014A
0.1 2/1/2007
[IBIS] ispPAC-POWR607
0.1 2/1/2007
[IBIS] ispPAC-POWR1220AT8
0.2 3/2/2012
[IBIS] ispPAC-POWR6AT6
0.1 2/1/2007
TITLE NUMBER VERSION DATE FORMAT SIZE
POWR1014A Breakout Board Demo Source
This demo includes the PAC-Designer project source for the preprogrammed demonstration design. It programs the POWR1014A with power supply enable sequence logic and a counter circuit using the embedded timer & open-drain digital pins configured for LED
1.0 3/21/2011
TITLE NUMBER VERSION DATE FORMAT SIZE
Selecting Power and Platform Manager Devices Excel Spreadsheet Tool
1.1 3/19/2012


サポート

Like most websites, we use cookies and similar technologies to enhance your user experience. We also allow third parties to place cookies on our website. By continuing to use this website you consent to the use of cookies as described in our Cookie Policy.