Platform Manager 2 & L-ASC10

Manage power, thermal & control planes in real time

Related Products


MachXO3

Reduced time to market – Fast and reliable fault detection/logging for power & thermal management and board control logic, coupled with simulation and in-system debug support.

Simple, scalable, end-to-end – Scalable platform for voltage, temperature, logic and I/O that can be easily expanded using L-ASC10 chips with glue-less interfaces.

Reduce BOM and cost – Designs across a wide range of systems can standardize on the Platform Manager 2 family instead of multiple single function ICs from multiple vendors.

Features

  • Full fault coverage – monitor all rails and temperature nodes
  • Manage from 10 to 80 supplies using just the required number of L-ASC10 hardware management expanders
  • Minimize fault propagation by enabling individual hardware management sub-blocks (power, thermal & control path) to respond to faults in other blocks within nano-seconds
  • Save CPLD I/O pins by eliminating the need to monitor power-good signals of DC-DC converters
  • Reliable power & thermal fault detection in hardware, as opposed to software routines

Jump to

Family Table

Platform Manager 2 Family

Parameters L-ASC10 LPTM21 LPTM21L
Voltage Monitoring Inputs 10 10 10
Current Monitoring Inputs 2 2 2
Temperature Monitoring Inputs 2 2 2
Number of Trimming Channels 4 4 4
MOSFET Drivers 4 4 4
Open Drain GPIO (5 V Tolerant) 9 10 10
On-Chip Non-Volatile Fault Log Check Mark Check Mark Check Mark
Number of LUTs - 1280 1280
Digital I/O Count (PIO) - 98 33
Primary Clock Inputs (PCLK) - 6 4
Distributed RAM (kBits) - 10 10
EBR SRAM (kBits) - 64 64
Number of EBR Blocks (9 kBits) - 7 7
User Flash Memory (kBits) - 64 64
Number of PLLs - 1 1
Communication I/F I2C I2C / JTAG I2C / JTAG
Programming Interface I2C I2C / JTAG I2C / JTAG
Operating Voltage 3.3 V 2.8 V to 12 V 3.3 V
Insystem Update Support Check Mark Check Mark Check Mark
Analog / Digital I/Os
Package Options L-ASC10 LPTM21 LPTM21L
48-pin QFN (7 X 7 mm2) 22 / 9 - -
100-Ball caBGA (10 X 10 mm2) - - 22 / 43
237-Ball ftBGA (17 X 17 mm2) - 22 / 108 -

Example Solutions

Control PLDExpand Image

Highly Scalable Hardware Management

  • Cut and paste solutions across a wide range of applications, and customize algorithms
  • Simplified board debug through an extensive suite of debug tools
  • Increased reliability with full fault coverage
  • Effortless integration of wide range of functions, such as temperature sense ICs, ADCs, reset generators, current sense ICs, and many digital buffers and controllers

Reduce CPLD I/O count

  • Save I/O pins by eliminating the need to monitor power-good signals of DC-DC converters as these status are available within the FPGA nodes
  • Save I/O pins that are used to monitor the power management circuitry control and monitor inputs
  • Save I/O pins used to communicate with microcontroller GPIO

Simplify thermal management by using PLD instead of software

  • Independent thermal faults detection in hardware as opposed to context switching software routines
  • Graceful degradation of services by combining the voltage and clock scaling with thermal faults
  • No need for thermal event communication between the CPLD and microcontroller

Reduce time to production - one design tool environment instead of 3 heterogeneous tools (Power Management GUI, VHDL/Verilog, C/ Assembly for microcontrollers)

  • Complete hardware management can be designed fully by either analog, or digital engineers, or both, using the LatticeDiamond Software through GUI or VHDL/ Verilog.
  • Fine tune power supply and reset sequencing without board modifications to enable reliable board start-up
  • Simulate the effects of different fault conditions (supply rail, thermal or control plane signals) using simple point-and-click software
  • Save development time and effort by reusing a single architecture for, scalable power management solution, scalable control plane function, thermal channels and interaction between them

Design Resources

Development Kits & Boards

Our development boards & kits help streamline your design process

Programming Hardware

Take the strain out of in-system programming & in-circuit reconfiguration with our programming hardware

Application Notes

Learn how to get the most from our line-up of FPGAs / development boards

Software

Complete Design Flows, High Ease of Use

Documentation

Quick Reference
Technical Resources
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
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Package Diagrams
FPGA-DS-02053 8.2 9/22/2024 PDF 9 MB
Extending the VMON Input Range of Power/Platform Management Devices
FPGA-AN-02031 2.5 9/21/2021 PDF 1.1 MB
Fault Logging Using Platform Manager 2
TN1277 2.1 1/5/2018 PDF 3.5 MB
Adding Scalable Power and Thermal Management to ECP5 Using L-ASC10
FPGA-AN-02019 1.2 8/7/2023 PDF 2 MB
Interfacing the Trim Output of Power Manager II Devices to DC-DC Converters
AN6074 1.2 4/7/2015 PDF 3.1 MB
Importing HDL Files With Platform Manager 2
TN1287 1.0 8/1/2014 PDF 546.9 KB
Implementing VID Function with Platform Manager 2
AN6092 1.2 9/8/2017 PDF 2.9 MB
Using Power MOSFETs with Power/Platform Management Devices
AN6048 1.3 8/29/2017 PDF 734.6 KB
Adding Scalable Power and Thermal Management to MachXO2 and MachXO3 Using L-ASC10
FPGA-AN-02011 1.2 10/11/2019 PDF 2.1 MB
Dual Boot and Background Programming with PlatformManager 2
FPGA-TN-02078 1.3 10/10/2019 PDF 1.9 MB
Platform Manager 2 PM Bus Adapter Usage
TN1297 1.0 2/11/2015 PDF 2.1 MB
Temperature Monitoring and Fan Control with Platform Manager 2
FPGA-TN-02080 1.2 9/30/2018 PDF 2.6 MB
L-ASC10 and Platform Manager 2 Hardware Checklist
FPGA-TN-02175 1.2 1/27/2020 PDF 1.1 MB
Powering Up and Programming Platform Manager 2 and L-ASC10
AN6091 2.1 3/31/2015 PDF 2 MB
Platform Manager 2 Data Sheet
FPGA-DS-02036 2.5 10/20/2023 PDF 2.8 MB
L-ASC10 Data Sheet
FPGA-DS-02038 2.5 8/3/2023 PDF 7 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Platform Manager 2 Data Sheet
FPGA-DS-02036 2.5 10/20/2023 PDF 2.8 MB
L-ASC10 Data Sheet
FPGA-DS-02038 2.5 8/3/2023 PDF 7 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Extending the VMON Input Range of Power/Platform Management Devices
FPGA-AN-02031 2.5 9/21/2021 PDF 1.1 MB
Fault Logging Using Platform Manager 2
TN1277 2.1 1/5/2018 PDF 3.5 MB
Adding Scalable Power and Thermal Management to ECP5 Using L-ASC10
FPGA-AN-02019 1.2 8/7/2023 PDF 2 MB
Interfacing the Trim Output of Power Manager II Devices to DC-DC Converters
AN6074 1.2 4/7/2015 PDF 3.1 MB
Importing HDL Files With Platform Manager 2
TN1287 1.0 8/1/2014 PDF 546.9 KB
Implementing VID Function with Platform Manager 2
AN6092 1.2 9/8/2017 PDF 2.9 MB
Using Power MOSFETs with Power/Platform Management Devices
AN6048 1.3 8/29/2017 PDF 734.6 KB
Adding Scalable Power and Thermal Management to MachXO2 and MachXO3 Using L-ASC10
FPGA-AN-02011 1.2 10/11/2019 PDF 2.1 MB
Dual Boot and Background Programming with PlatformManager 2
FPGA-TN-02078 1.3 10/10/2019 PDF 1.9 MB
Platform Manager 2 PM Bus Adapter Usage
TN1297 1.0 2/11/2015 PDF 2.1 MB
Temperature Monitoring and Fan Control with Platform Manager 2
FPGA-TN-02080 1.2 9/30/2018 PDF 2.6 MB
L-ASC10 and Platform Manager 2 Hardware Checklist
FPGA-TN-02175 1.2 1/27/2020 PDF 1.1 MB
Powering Up and Programming Platform Manager 2 and L-ASC10
AN6091 2.1 3/31/2015 PDF 2 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Package Diagrams
FPGA-DS-02053 8.2 9/22/2024 PDF 9 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Platform Manager 2 Evaluation Board User Guide
EB93 1.0 1/1/0001 PDF 7.3 MB
Platform Manager 2 I2C Demo Design and GUI
UG59 1.1 8/11/2017 PDF 5.2 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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MachXO2/MachXO3/LPTM21 WISHBONE Flash Corruption Avoidance
PB1381 1.1 1/3/2017 PDF 88.9 KB
Work-around Solution for Platform Manager 2, MachXO2, and MachXO3 in SPI Programming Failure Modes
PB231101 1.0 1/11/2024 PDF 372.2 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
PCN01A-15: LPTM20 Withdrawal
Data Sheet 		PCN01A-15 4/28/2015 PDF 123.4 KB
PCN 09A-16_L-ASC10 I2C Datasheet
Data Sheet 		PCN09A-16 6/13/2016 PDF 96.9 KB
Power Calculator Update for All XO2 and Derivative (XO2/XO3L/XO3LF/XO3D/PlatformManager2) Devices
PCN02A-20 1.1 1/14/2021 PDF 28.6 KB
PCN01A-18 - L-ASC10 and LPT2M Alternate Qualified Mask Set
PCN01A-18 A 4/18/2018 PDF 209.9 KB
PCN08A-19 Platform Manager 2 and L-ASC10 Data sheet Update
1.0 10/1/2019 PDF 285.3 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Lattice OrCAD Capture Schematic Library (OLB)
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs. 		FPGA-SC-02005 8.2 8/8/2024 ZIP 2.6 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Platform Manager 2 Brochure
I0236 2.0 4/21/2017 PDF 2.6 MB
Product Selector Guide
I0211 46.0 7/18/2024 PDF 9.7 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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FTG237_LPTM21
Rev J1 6/9/2022 PDF 141.9 KB
SN_SG48
Rev C1 9/20/2019 PDF 52.9 KB
TG128_DD
Rev D 4/13/2018 PDF 22.1 KB
Lattice Platform Manager 2 Product Family Qualification Summary
Rev F 4/15/2020 PDF 729.9 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Revolutionary Hardware Management Solutions
WP0003 4.0 5/9/2018 PDF 1.4 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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LPTM21_ftbga237
1.0 12/1/2014 BSM 29.3 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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[IBIS] L-ASC10
1.1 7/21/2020 IBS 116.6 KB
[IBIS] LPTM21
1.0 5/27/2015 ZIP 9.8 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Platform Manager 2 I2C GUI
1.1 10/7/2014 ZIP 3.3 MB

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