Platform Manager 2 & L-ASC10

Manage power, thermal & control planes in real time

Reduced time to market – Fast and reliable fault detection/logging for power & thermal management and board control logic, coupled with simulation and in-system debug support.

Simple, scalable, end-to-end – Scalable platform for voltage, temperature, logic and I/O that can be easily expanded using L-ASC10 chips with glue-less interfaces.

Reduce BOM and cost – Designs across a wide range of systems can standardize on the Platform Manager 2 family instead of multiple single function ICs from multiple vendors.


  • Full fault coverage – monitor all rails and temperature nodes
  • Manage from 10 to 80 supplies using just the required number of L-ASC10 hardware management expanders
  • Minimize fault propagation by enabling individual hardware management sub-blocks (power, thermal & control path) to respond to faults in other blocks within nano-seconds
  • Save CPLD I/O pins by eliminating the need to monitor power-good signals of DC-DC converters
  • Reliable power & thermal fault detection in hardware, as opposed to software routines

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Family Table

Platform Manager 2 Family

Parameters L-ASC10 LPTM21 LPTM21L
Voltage Monitoring Inputs 10 10 10
Current Monitoring Inputs 2 2 2
Temperature Monitoring Inputs 2 2 2
Number of Trimming Channels 4 4 4
MOSFET Drivers 4 4 4
Open Drain GPIO (5 V Tolerant) 9 10 10
On-Chip Non-Volatile Fault Log Check Mark Check Mark Check Mark
Number of LUTs - 1280 1280
Digital I/O Count (PIO) - 98 33
Primary Clock Inputs (PCLK) - 6 4
Distributed RAM (kBits) - 10 10
EBR SRAM (kBits) - 64 64
Number of EBR Blocks (9 kBits) - 7 7
User Flash Memory (kBits) - 64 64
Number of PLLs - 1 1
Communication I/F I2C I2C / JTAG I2C / JTAG
Programming Interface I2C I2C / JTAG I2C / JTAG
Operating Voltage 3.3 V 2.8 V to 12 V 3.3 V
Insystem Update Support Check Mark Check Mark Check Mark
Analog / Digital I/Os
Package Options L-ASC10 LPTM21 LPTM21L
48-pin QFN (7 X 7 mm2) 22 / 9 - -
100-Ball caBGA (10 X 10 mm2) - - 22 / 43
237-Ball ftBGA (17 X 17 mm2) - 22 / 108 -

Example Solutions

Highly Scalable Hardware Management

  • Cut and paste solutions across a wide range of applications, and customize algorithms
  • Simplified board debug through an extensive suite of debug tools
  • Increased reliability with full fault coverage
  • Effortless integration of wide range of functions, such as temperature sense ICs, ADCs, reset generators, current sense ICs, and many digital buffers and controllers

Reduce CPLD I/O count

  • Save I/O pins by eliminating the need to monitor power-good signals of DC-DC converters as these status are available within the FPGA nodes
  • Save I/O pins that are used to monitor the power management circuitry control and monitor inputs
  • Save I/O pins used to communicate with microcontroller GPIO

Simplify thermal management by using PLD instead of software

  • Independent thermal faults detection in hardware as opposed to context switching software routines
  • Graceful degradation of services by combining the voltage and clock scaling with thermal faults
  • No need for thermal event communication between the CPLD and microcontroller

Reduce time to production - one design tool environment instead of 3 heterogeneous tools (Power Management GUI, VHDL/Verilog, C/ Assembly for microcontrollers)

  • Complete hardware management can be designed fully by either analog, or digital engineers, or both, using the LatticeDiamond Software through GUI or VHDL/ Verilog.
  • Fine tune power supply and reset sequencing without board modifications to enable reliable board start-up
  • Simulate the effects of different fault conditions (supply rail, thermal or control plane signals) using simple point-and-click software
  • Save development time and effort by reusing a single architecture for, scalable power management solution, scalable control plane function, thermal channels and interaction between them

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Application Notes

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