The AXI Register Slice core connects one AXI standard manager to one AXI standard subordinate by introducing pipeline stages in between the two to close timing in critical paths. Different configuration options are available. Each AXI channel transfers information in only one direction and the architecture does not require a fixed relationship between the channels. The user can insert a register slice at almost any point in any channel, with an additional cycle of latency.
Uses Simple Register Slices for a Direct and Fast Connection – This IP core allows direct, fast connection between a processor and high-performance memory, by using simple register slices to isolate the longer path to less performance critical peripherals.
Latency Cycles and Maximum Operation Frequency Trade-Off – This IP core also allows trade-off between cycles of latency and the maximum frequency of operation.