10Gb Ethernet MAC+PHY IP Core

Ethernet Transmission of Data Frame Compliant to the IEEE 802.3-2012 Standard

Related Products

The Lattice Semiconductor 10G Ethernet (GbE) IP core supports the ability to transmit and receive data between a host processor and an Ethernet network. The 10GbE IP core consists of the 10-Gigabit Media Independent Interface (XGMII), which connects media access controllers (MACs) and Physical Layer devices (PHYs).

This IP Core is supported in the Lattice Avant™-G, Lattice Avant™-X FPGA for both the MAC, PHY and MAC & PHY combos. For CertusPro™-NX device family, the MAC, PHY and MAC + PHY + 1588 options are available. These options are available in the Lattice Radiant™ software.

Resource Utilization details are available in the IP Core User Guide.

Features

MAC

  • Compliant to the IEEE 802.3-2012 standard
  • Supports standard 10 Gbps Ethernet link layer data rate
  • 64-bit wide internal datapath operating at 156.25 MHz
  • AXI4-Stream interface on the client’s transmit and receive interfaces

PHY

  • Designed to the IEEE 802.3-2012 10GBASE-R specification
  • 64b/66b encoding and decoding
  • XGMII interface: 64-bit, 156.25 MHz
  • Supports AXI4-Lite and management data input/output (MDIO) interfaces for PCS/PMA and MDIO manageable device (MMD) register access

MAC + PHY + 1588 (CertusPro™-NX)

  • Supported APB register access
  • Timestamping support as specified in the IEEE 1588v2 (2-step mode)

Jump to

Block Diagram

10Gb Ethernet MAC+PHY IP Core Block DiagramExpand Image

Resource Utilization

Avant Devices (ES)
Configuration Registers LUTs EBRs Target Device Synthesis Tools
PHY Only
Host Interface == AXI4-Lite		 755 (<1%) 1,231 (<1%) 0 (0%) LAV-AT-G70ES Synplify Pro
PHY Only
Host Interface == APB		 728 (<1%) 1,134 (<1%) 0 (0%) LAV-AT-G70ES Synplify Pro
PHY Only
Host Interface == MDIO		 815 (<1%) 1,347 (<1%) 0 (0%) LAV-AT-G70ES Synplify Pro
MAC + PHY
Host Interface == AXI4-Lite		 4,021 (1%) 5,749 (1%) 3 (<1%) LAV-AT-G70ES Synplify Pro
MAC + PHY
Multicast Address Filtering == Enabled
Statistics Counter Registers == Enabled
Counter Width == 32
Host Interface == AXI4-Lite		 7,592 (2%) 8,926 (2%) 3 (<1%) LAV-AT-G70ES Synplify Pro
MAC + PHY
Multicast Address Filtering == Enabled
Statistics Counter Registers == Enabled
Counter Width == 64
Host Interface == AXI4-Lite		 11,048 (3%) 11,921 (3%) 4 (<1%) LAV-AT-G70ES Synplify Pro
CertusPro-NX and Avant Devices (non ES)
Configuration Registers LUTs EBRs Target Device Synthesis Tools
PHY Only 36 (<1%) 43 (<1%) 0 (0%) LFCPNX-100 Synplify Pro
MAC + PHY + 1588 14,767 (18%) 11,397 (14%) 16 (8%) LFCPNX-100 Synplify Pro
PHY Only
Host Interface == AXI4-Lite		 126 (<1%) 179 (<1%) 4 (2%) LAV-AT-G70 Synplify Pro
PHY Only
Host Interface == APB		 99 (<1%) 80 (<1%) 0 (0%) LAV-AT-G70 Synplify Pro
PHY Only
Host Interface == MDIO		 186 (<1%) 271 (<1%) 0 (0%) LAV-AT-G70 Synplify Pro
MAC + PHY
Host Interface == AXI4-Lite		 3,362 (1%) 4,670 (1%) 3 (<1%) LAV-AT-G70 Synplify Pro
MAC + PHY
Multicast Address Filtering == Enabled
Statistics Counter Registers == Enabled
Counter Width == 32
Host Interface == AXI4-Lite		 7,001 (2%) 8,082 (2%) 3 (<1%) LAV-AT-G70 Synplify Pro
MAC + PHY
Multicast Address Filtering == Enabled
Statistics Counter Registers == Enabled
Counter Width == 64
Host Interface == AXI4-Lite		 10,251 (3%) 10,967 (3%) 3 (<1%) LAV-AT-G70 Synplify Pro
MAC Only
Multicast Address Filtering == Enabled		 3,275 (1%) 4,554 (1%) 3 (<1%) LAV-AT-G70 Synplify Pro
MAC Only
Multicast Address Filtering == Enabled
Statistics Counter Registers == Enabled
Counter Width == 64		 10,383 (3%) 10,789 (3%) 3 (<1%) LAV-AT-G70 Synplify Pro

Ordering Information

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
Avant-G ETHER-10G-AVG-UT ETHER-10G-AVG-US
Avant-X ETHER-10G-AVX-UT ETHER-10G-AVX-US
CertusPro-NX ETHER-10G-CPNX-UT ETHER-10G-CPNX-US

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
10G Ethernet Driver API Reference
FPGA-TN-02375 1.0 7/30/2024 PDF 485.8 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
10G Ethernet MAC + PHY IP Core - User Guide
FPGA-IPUG-02245 1.3 9/10/2024 PDF 4.5 MB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

ABOUT LATTICE

SALES

SUPPORT

FOLLOW