RISC-V MC CPU IP Core

RISC-V for Micro-Controller Applications

The Lattice Semiconductor RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC). The CPU core is with instruction and data caches. The CPU core supports RV32IMC instruction set, external interrupts, and debug feature that is JTAG – IEEE 1149.1 compliant. The Timer submodule is a 64-bit real time counter, which compares a real-time register with another register to assert the timer interrupt. The PIC submodule aggregates up to eight external interrupt inputs into one external interrupt. The submodule registers are accessed by the processor core using a 32-bit Advanced High-performance Bus – Lite (AHB-L) interface.

The design is implemented using Verilog HDL, and it can be configured and generated using the Lattice Propel™ Builder software. It supports Lattice Avant™, MachXO5™-NX, Certus™-NX, CertusPro™-NX, CrossLink™-NX, MachXO3D™, MachXO3™, and MachXO2™ FPGA devices.

Processing Data and Monitoring External Interrupts Simultaneously - It uses one AHB-L interface (Read-Only) for instruction fetch and another AHB-L interface (Read/Write Access) for data access.

PIC and Timer Submodules - The CPU soft IP contains submodules: PIC and Timer. The PIC and Timer share the same start address in the memory map and a fixed two KB address range is allocated, if either PIC or Timer is enabled.

Features

  • RV32IMC instruction set
  • Five stages of pipelines
  • Support the AHB-L bus standard for instruction/data port
  • Optional caches, including a 4 KB two-way instruction cache and a 4 KB two-way data cache (for Lattice Avant, MachXO5-NX, Certus-NX, CertusPro-NX, and CrossLink-NX only)
  • Optional debug using Gnu Debugger (GDB) and Open On-Chip Debugger (OpenOCD)

Block Diagram

Resource Utilization

Lattice Avant Device (with Cache Disabled)
Configuration LUTs Registers EBRs DSPs
Processor core only 2015 867 2 0
Processor core + PIC 2097 886 2 0
Processor core + Timer 2456 979 2 0
Processor core + Debug 2376 1268 2 0
Processor core + C_EXT 2202 860 2 0
Processor core + C_EXT + M_EXT 2731 1284 2 6
Processor core + PIC + Timer 2535 1017 2 0
Processor core + PIC + Timer + Debug 2869 1444 2 0
Processor core + PIC + Timer + Debug + C_EXT 3128 1528 2 0

Note: Resource utilization characteristics are generated using Lattice Radiant software.

Lattice Avant Device (with Cache Enabled)
Configuration LUTs Registers EBRs DSPs
Processor core only 3340 1364 18 0
Processor core + PIC 3437 1406 18 0
Processor core + Timer 3857 1548 18 0
Processor core + Debug 3708 1806 18 0
Processor core + C_EXT 3671 1546 18 0
Processor core + C_EXT + M_EXT 4431 1861 18 6
Processor core + PIC + Timer 3809 1655 18 0
Processor core + PIC + Timer + Debug 4381 1995 18 0
Processor core + PIC + Timer + Debug + C_EXT 4559 2168 18 0

Note: Resource utilization characteristics are generated using Lattice Radiant software.

CertusPro-NX Device (with Cache Disabled)
Configuration LUTs Registers EBRs DSPs
Processor core only 1978 834 2 0
Processor core + PIC 2105 886 2 0
Processor core + Timer 2446 990 2 0
Processor core + Debug 2304 1218 2 0
Processor core + C_EXT 2288 896 2 0
Processor core + C_EXT + M_EXT 2790 1185 2 6
Processor core + PIC + Timer 2578 1032 2 0
Processor core + PIC + Timer + Debug 2871 1390 2 0
Processor core + PIC + Timer + Debug + C_EXT 3220 1461 2 0

Note: Resource utilization characteristics are generated using Lattice Radiant software.

CertusPro-NX Device (with Cache Enabled)
Configuration LUTs Registers EBRs DSPs
Processor core only 3031 1461 20 0
Processor core + PIC 3391 1505 20 0
Processor core + Timer 3812 1607 20 0
Processor core + Debug 3667 1854 20 0
Processor core + C_EXT 3691 1613 19 0
Processor core + C_EXT + M_EXT 4334 2007 19 6
Processor core + PIC + Timer 3926 1671 20 0
Processor core + PIC + Timer + Debug 4139 2012 20 0
Processor core + PIC + Timer + Debug + C_EXT 4450 2169 19 0

Note: Resource utilization characteristics are generated using Lattice Radiant software.

To view the complete Resource Utilization of the RISC-V MC IP Core, click here to view the table.

Documentation

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