1 Input to 2 Output MIPI DSI Display Splitter Bridge

Important: For new designs, Lattice recommends using the following modular IP blocks to implement this function:

The following Reference Design provides an integration example using these modular IP blocks

Many new applications such as virtual reality, augmented reality, and digital cameras require expansion of the number of display interfaces on applications processors. This often occurs when there is either not enough ports or some ports are used for other purposes on the application processor. Common examples are splitting one MIPI DSI port to two MIPI DSI ports and driving two displays. Another example is driving a high resolution display with two DSI ports with a single higher speed MIPI DSI interface.

Lattice CrossLink is a programmable video interface bridging device capable of providing multiple MIPI DSI interfaces at up to 6 Gbps per PHY. This bridge is available as free IP is available in Lattice Diamond for allowing easy configuration and setup.


  • Supports MIPI DSI up to 6 Gbps per MIPI D-PHY
    • 1, 2 or 4 Data Lanes
  • Provides one or two MIPI DSI outputs
    • MIPI DSI data replicated to each output port
  • Supports all MIPI DSI data types
    • RGB, YCbCr, User Defined
  • Provides a DCS (Display Command Set) controller to program the display, ROM data used only for DSI in HS or LPDT mode – ROM is programmable by user
  • Compliance with MIPI D-PHY Specification v1.1
  • Compliance with DSI Specification v1.1

Block Diagram

One Input to Two Output MIPI DSI Display Splitter Bridge Block Diagram


Quick Reference
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1:2 and 1:1 MIPI DSI Display Interface Bridge Soft IP User Guide
FPGA-IPUG-02001 1.4 5/10/2019 PDF 2.4 MB

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