Common Public Radio Interface - IP Core

IP ExpressThis document provides technical information about the Lattice Common Public Radio Interface (CPRI) IP core. This IP core together with SERDES and Physical Coding Sublayer (PCS) functionality integrated in the LatticeECP3™ and ECP5™ LFE5UM FPGAs implements the physical layer of the CPRI specification and interleaves IQ data with synchronization, control and management information. It can be used to connect Radio Equipment Control (REC) and Radio Equipment (RE) modules.

The CPRI IP core implements not only all of the capabilities required to support the physical layer of the CPRI specification (basic function), but also specific requirements related to link delay accuracy (low latency character).

One CPRI core configuration for 5G version (4.9152 Gbps) is also supported. It is similar to the "low latency" one for 3G version except the data rate.


  • Supports the physical link layer (Layer 1) of the CPRI specification
  • Supports five standard bit rates of the CPRI specification
    • 614.4 Mbps
    • 1228.8 Mbps
    • 2457.6 Mbps
    • 3072 Mbps
    • 4915.2 Mbps
  • Supports 8b/10b encoding/decoding performed in the PCS/SERDES
  • Supports code-violation detection performed in the PCS/SERDES
  • Performs CPRI Hyperframe Framing
    • Performs interleaving of IQ data, sync, C&M data, and vendor specific information
    • Provides an 8-, 16-, or 32-bit parallel interface for IQ data
  • Performs subchannel mapping:
    • Supports a slow C&M channel based on a serial HDLC interface at standard bit rates (240 Kbps, 480 Kbps,960 Kbps, and 1920 Kbps). The HDLC framer, if needed, must be provided as a separate IP core.
    • Supports a fast C&M channel based on a serial Ethernet interface (84.48 Mbps max.) to the user logic, anon-standard rate MII Ethernet interface to a MAC, or a 100 Mbps MII interface to a PHY device. Accepts a user-selected pointer to the CPRI subchannel where the Ethernet link starts. The Ethernet MAC function isprovided as a separate IP core.
  • Performs synchronization and timing as defined in section 4.2.8 of the CPRI Specification
  • Supports the L1 Inband Protocol
  • Provides a parallel interface for merging vendor specific data into the CPRI frame
  • Provides a start-up sequence state machine in hardware for both REC and RE nodes which performs:
    • Synchronization and Rate Negotiation
    • C&M Plane setup
  • Performs Link Maintenance as defined in section 4.2.10 of the CPRI Specification:
    • LOS detection
    • LOF detection
    • RAI indication
  • Optional top-level template that implements user registers for control and status management
  • Optional 8-bit register interface through the JTAG port

Jump to

Block Diagram

Common Public Radio Interface Core IP CPRI Serdes/PCS

Performance and Size

CPRI IP Core (3G Version)
Across All IP Configurations
FPGA Families Supported LatticeECP3, ECP5
Minimal Device Supported LFE3-35E-6FTN256C LFE5UM-85F-7MG381C
Data Path Width 8 - 40 bits
LUTs 1400 - 1600 1600 - 2000
sysMEM™ EBRs 2 - 6
Registers 1500 - 1700 1500 - 1700
CPRI IP Core (5G Version)
  Across All IP Configurations
FPGA Families Supported ECP5-5G
Minimal Device Supported LFE5UM5G-45F-8BG381C
Data Path Width 64 bits
LUTs 1100 - 1600
sysMEM EBRs 2 - 6
Registers 1000 - 1300

Ordering Information

Family Part Number
LatticeECP3 CPRI-E3-U4
LatticeSC/M CPRI-SC-U4

IP Version: 3.3

Evaluate: To download a full evaluation version of this IP, go to the IPexpress tool and click the IP Server button in the toolbar. All LatticeCORE IP cores and modules available for download will be visible. For more information on viewing/downloading IP please read the IP Express Quick Start Guide.

Purchase: To find out how to purchase the IP Core, please contact your local Lattice Sales Office.


Quick Reference
Information Resources
Select All
CPRI IP Core User Guide Low Latency Addendum
IPUG74 01.5 11/12/2009 PDF 662 KB
CPRI IP Core User Guide
IPUG56 2.8 7/13/2017 PDF 2.4 MB
Select All
IPexpress Quick Start Guide
8/5/2010 PDF 304.8 KB

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