DDR3 SDRAM Controller

General Purpose DDR3 Memory Interface Controller

The Lattice Double Data Rate Synchronous Dynamic Random Access Memory (DDR3 SDRAM) Controller IP Core is a general-purpose memory controller that interfaces with industry standard DDR3 memory devices compliant with JESD79-3C, DDR3 SDRAM Standard. This IP provides a generic command interface to user applications.

This IP supports the following Nexus devices in Lattice Radiant: CrossLink™-NX, Certus™-NX, Mach™-NX, and CertusPro™-NX. It also supports the ECP5 and LatticeECP3 devices in Lattice Diamond.

Resource Utilization details are available in the DDR3 SDRAM Controller (Lattice Radiant) and DDR3 SDRAM Controller (Lattice Diamond) User Guides.

Features

Nexus

  • Memory data path widths of 8, 16, 24, 32 bits (x24 is only for Bus Interface Type = NATIVE).
  • Selectable gearing ratios: 4:1, 8:1
    • *533 MHz/1066 Mbps is only supported for 8:1 gearing
    • *4:1 gearing is supported up to 400 MHz/800 Mbps, except for speed grades 7 and 8 (limited to 333 MHz/666 Mbps)
  • x8 and x16 device configurations
  • Programmable burst lengths of 8 (fixed), chopped 4 or 8 (on-the-fly), or chopped 4 (fixed)

ECP5 and LatticeECP3

  • Memory data path widths of 8, 16, 24, 32, 40, 48, 56, 64, and 72 bits
  • x4, x8, and x16 device configurations
  • Interfaces to DDR3 SDRAM at speeds of up to 400 MHz/800 Mbps in speed grade 8 ECP5 devices and speed grade 9 LatticeECP3 devices
  • Programmable burst lengths of 8 (fixed), chopped 4 or 8 (on-the-fly), or chopped 4 (fixed)

Jump to

Block Diagram

  • DDR3 SDRAM Controller IP Core diagram for Nexus devices
  • High-level block diagram illustrating the main functional block used to implement the DDR3 SDRAM Controller IP Core functions
  • DDR3 SDRAM Controller IP Core diagram for ECP5 and LatticeECP3 devices
  • The DDR3 memory controller consists of 3 sub modules: Memory Controller (MC) module, Physical Interface (PHY) module, and Clock Synchronization Module (CSM)

Comparison Table

The table outlines the differences between the Lattice Nexus platform and the older LatticeECP5 and LatticeECP3 FPGA families in terms of speed, data widths, and configuration options.

Lattice Device/Platform Nexus ECP5 LatticeECP3
Max Interface Speed 400 MHz / 800 Mbps 400 MHz / 800 Mbps 400 MHz / 800 Mbps
Supported Data Widths -8, -16, -24, -32 -8, -16, -24, -32, -40, -8, -16, -24, -32, -40, -48, -56, -64, -72
-48, -56, -64, -72
Supported Device Configurations x8, x16 x4, x8, x16 x4, x8, x16
Supported Memory Format Component Component, DIMM, RDIMM Component, DIMM, RDIMM

Ordering Information

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
CertusPro-NX DDR3-P-CPNX-UT DDR3-P-CPNX-U
CrossLink-NX DDR3-P-CNX-UT DDR3-P-CNX-U
Certus-NX DDR3-P-CTNX-UT DDR3-P-CTNX-U
MachXO5-NX DDR3-XO5-UT DDR3-XO5-US

IP Version: 1.4.

Evaluate: To download a full evaluation version of this IP, go to the IPexpress tool and click the IP Server button in the toolbar. All LatticeCORE IP cores and modules available for download will be visible. For more information on viewing/downloading IP please read the IP Express Quick Start Guide.

Purchase: To find out how to purchase the IP Core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
DDR3 SDRAM Controller IP Core - Lattice Diamond Software
FPGA-IPUG-02047 2.2 10/11/2020 PDF 3.6 MB
DDR3 SDRAM Controller IP Core for Nexus Devices
FPGA-IPUG-02086 1.8 12/20/2024 PDF 1.8 MB
LatticeECP3 DDR3 Demo for the LatticeECP3 I/O Protocol Board User's Guide
UG38 01.4 6/8/2012 PDF 2.7 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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DDR3 SDRAM Controller IP Release Notes
FPGA-RN-02032 1.0 12/20/2024 PDF 403.3 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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IPexpress Quick Start Guide
8/5/2010 PDF 304.8 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Implementing DDR3 Memory Controller (LatticeECP3)
1.0 3/10/2010 PDF 147.9 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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LatticeECP3 DDR3 Demo
1.4 6/8/2012 ZIP 235.3 KB

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