Lattice Blog


Interfacing with SPI Devices, Part 2

Posted 09/23/2021 by Eugen Krassin

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“The LEC2 Workbench” is an ongoing series of technical blog posts focused on application development using Lattice products. The posts are authored by FPGA design experts from the Lattice Education Competence Center (LEC2), the official global provider of training services focused exclusively on Lattice’s award-winning low power FPGAs and solution stacks.

Lattice CrossLink™-NX FPGAs have a rich feature set to accelerate the implementation of high and low speed interfaces. This blog (the second in a two part series) describes the implementation of interfaces to SPI-based external components using CrossLink-NX FPGAs. This first blog described the implementation of a SPI interface using two clock domains. This blog will describe the implementation of a SPI interface to an ADC (the AD7476 from Analog Devices) using a single clock domain. In both cases, two fundamentally different approaches to implementing the interface are presented.

One clock domain implementation (dac_1c)
The implementation of the single clock SPI interface is shown in Figure 1.

Figure 1: Implementation of single clock domain SPI interface

The concept of the single clock domain SPI implementation is quite similar to the two clock domain implementation. For illustration purposes the PLL is not used. Also, the module sync_stage is not needed. Because of the single clock, the module clock_generator is needed to signal the falling edge condition of the dac_sck which is used as a trigger condition for state machine dac_fsm.

Module clock_generator

The module clock_generator as shown in Figure 2 generates the clock signal dac_clk as well as the indication of falling edge of dac_sck. Figure 3 shows the relationship if dac_sclk and edge_low.


Figure 2: Block diagram of module clock_generator

Figure 3: Control Structure for the on clock domain dac_fsm State Machine.
After the convert signal has been recognized, the bit_count counter is loaded with the value 15. The serial data are output on the dac_sdata line with the rising edge of the clock signal CLK_120 whenever edge_low is asserted. After 16 data bits have been transmitted, dac_fsm de signals readiness again and waits for the next convert signal.

Constraining the Design for the one clock domain solution

1. Constraining the clock CLK¬120

2. Constraining the dac_clk
The clock signal connected to port dac_sck is generated by the clock_generator. The relationship between CLK_120 and dac_sck is divide by 4.

3. Constraining the DAC Inputs/FPGA Outputs
Time values t4, t5 and t6 describe the setup / hold requirements for the external module. These requirements are described with the set_output_delay constraint. Because of the single clock domain, a multicycle specification is needed.

Running the Timing Analysis for one clock domain solution
As expected, the timing analysis report shows identical performance data on the dac_sdata output signal.



The single clock domain concept uses a single clock distribution network, which provides a design advantage because no sync stages are needed to communicate with high level functions.

Both this project (dac-1c) and the two domain projects (dac_2c) are available on request at

Eugen Krassin is President and Founder of the Lattice Education Competence Center (LEC2).