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The Importance of Partnerships: Lattice and our IP Partners

The Importance of Partnerships: Lattice and our IP Partners
Posted 05/01/2018 by Jatinder (JP) Singh

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There is an old saying that two heads are better than one, and nothing could be truer when it comes to strategic partnerships. In today’s business environment, partnerships are of the greatest value to organizations that are focused on supporting the end-customers. Partners must have synergies and enhance the collective value proposition to bring benefits to the customer. The partners should work together to strengthen their respective businesses either through knowledge transfer or capacity building.

For an FPGA company like Lattice, requests for different functions from different market segments are very common. Many of these applications require some standard functionality that can be implemented in the FPGA. Some of these functions can be standard, while others may be very unique and specific to the industry. These vary from networking IPs, like Local Interconnect Network (LIN) and Controller Area Network for the automotive segment, to High Definition Range Image Signal Processing (HDR ISP) for cameras and displays, and DisplayPort compliant interfaces for the modern LCD panels for industrial and consumer segments. All of these IPs are very unique and require the organizations to invest into acquiring knowledge and expertise. By partnering with organizations that are experts in such IPs allows companies to bring the capability and overall value to the end-customers faster.

Over the past couple of years, we have joined hands with a number of IP design partners to bring the often requested capabilities to a variety of low-power, production-priced FPGAs. The IPs available from our third-party ecosystem provide support for a variety of products ranging from world’s smallest iCE40 FPGA series, to the very capable, lowest-power, SERDES-based FPGAs like ECP5. These partners have been carefully selected based on a variety of IPs of interest, along with licensing models, support structure, and ease of integration into the end-system. In this blog, I would like to discuss, some of our newest software-based IP partnerships that are bringing new functions and capabilities to our FPGAs.

CAST, Inc.

One of our oldest partners, CAST, Inc., has been in business for more than a decade and a half. They provide a variety of pre-designed and pre-verified IP cores that save on development time and add functionality. Their key mantra is to enable design reuse methodology, which keeps the overhead costs low, and they are a very user-focused organization that is highly committed to customer satisfaction and support. They are always eager to port any of their IPs to Lattice FPGAs. Here are few that they have recently made available.

Controller Area Network Controller

Originally proposed in the 1980s by Robert Bosch GmbH, Controller Area Network (CAN) was a widely used automotive networking standard before it’s standardization by ISO in 1993. As the need for faster data rates grew, Bosch took an active initiative in extending it to CAN 2.0 and CAN-FD (flexible data rate). CAN is extensively used in a modern vehicles, which may have as many as 70 electronic control units (ECU) for various subsystems. Engine control unit, transmission, airbags, antilock braking/ABS, cruise control, electric power steering, audio systems, power windows, doors, mirror adjustment, battery and recharging systems for hybrid/electric cars are some of the examples of the system that communicate over CAN bus.

CAST’s CAN Controller IP core has been available for a variety of Lattice FPGAs. CAN protocol bus controller performs serial communication according to CAN 2.0 and CAN FD specifications. It supports the original Bosch protocol and ISO specifications as defined in ISO 1989, including time-triggered operation (TTCAN) as specified in ISO 19898-4. It is also optimized to support the popular AUTOSAR and SAE J1939 specifications.

CAST-CAN Block Diagram

Local Interconnect Network (LIN)

LIN is one of the oldest networking protocols on the automotive platform. It is a serial network protocol used for communication between components in vehicles. The need for the cheap serial network (compared to CAN) arose as the technologies and the facilities implemented in the car grew. During the 1990s, the LIN Consortium was founded by five automakers (BMW, Volkswagen Group, Audi Group, Volvo Cars, Mercedes-Benz), with the technologies supplied (networking and hardware expertise) from Volcano Automotive Group and Motorola. What is most interesting is that this technology is still used in today’s cars for sensor lights/ icons like a seat belt, cruise control, climate control, radio, small motors, and control panels.

CAST’s LIN Controller core offers a microcode-free design developed for reuse in FPGA implementations. This core can be configured for master or slave functionality, and has been tested, verified and has been in production.

CAST-LIN Block Diagram

JPEG Compression IP Cores (Baseline and Extended)

All of us are aware of the JPEG or JPG files for our photographs. If you have used a digital camera that allows RAW format images, you probably know that the file size can be almost 10x the size of the JPEG file. It is a commonly used method, albeit a lossy compression for digital images, where the degree of compression can be adjusted, allowing a selectable tradeoff between storage size and image quality.

CAST has two IP cores for the hardware-based JPEG compression. The JPEG-E-S Encoder produces compressed JPEG images and the video payload for Motion-JPEG container formats. It accepts images with 8-bit color samples and up to four color components, in all widely-used color subsampling formats. Customers with a short time to market priority can use CAST’s IP Integration Services to receive complete JPEG subsystems. The core is designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. Its deliverables include a complete verification environment and a bit-accurate software model.

CAST-JPEG-EX-S Block Diagram

Helion Vision, GmbH

Helion Vision, a company founded in 2003, offers more than 15 years of experience in image pre-processing-ISP and adds special knowledge of High Dynamic Range (HDR) image processing to the fields of automotive, medical, security and industrial. They have implemented and designed advanced IP-Cores for real-time image pre- and post-processing in FPGA devices.

Lattice and Helion Vision have worked together in the past on IONOS Image Signal Processing (ISP) for LatticeECP3 devices. Now, we have brought this state-of-the-art ISP pipeline to our ECP5 devices.

IONOS Image Signal Processing

Helion Vision’s IONOS IP cores provide plug and play processing solutions utilizing a library of over 100 individual IP cores. IONOS provides pre-configured, ready-to-use ISP by utilizing a portfolio of IP cores for customized camera systems, imaging modules, and complete camera and display systems for the automotive, medical, security and industrial markets. With over a decade of experience in research and development, Helion Vision offers a wide variety of design services to make camera development efficient, fast and agile.

Embedded Vision Systems Block Diagram

Helion Vision's IONOS ISP is a user-configurable ISP Pipeline IP, and is image sensor interface independent. It also supports various transmit interfaces to panels, applications processors or SoCs.

IONOS Image Signal processing IP Pipelines

Bitec Spain SL

One of Lattice’s recent partnerships has been with BITEC for a popular display interface – DisplayPort. Bitec was founded in 2002 with the aim of providing high-quality technology advice to customers worldwide. Bitec is headquartered in Marbella, Spain. In more than 10 years of activity, BITEC has conducted numerous international projects of large-scale research, development and innovation worldwide both consulting (developing projects for clients) as well as internally, having repeatedly taken concepts to production.

DisplayPort 1.4a IP Core

DisplayPort (DP) is a digital display interface developed by a consortium of PC and chip manufacturers, and standardized by the Video Electronics Standards Association (VESA). The interface is primarily used to connect a video source to a display device such as a computer monitor, and it can also carry audio, USB, and other forms of data. DisplayPort was designed to replace VGA, DVI, and FPD-Link and provides backward compatibility with other interfaces, such as HDMI and DVI.

The Bitec DisplayPort IP core for ECP5 FPGAs enables manufacturers to rapidly develop and deliver displays offering a superior viewing experience within ever-shrinking product lifecycles. The IP core accepts 1, 2 or 4 lanes at either 1.62 or 2.7 Gbps link rate, in compliance with the DisplayPort 1.4 specification. The core is also embedded DisplayPort (eDP) compatible and includes eDP additional rates.

Supporting resolutions of up to 1080p60, it is available in both transmitter (Tx) and receiver (Rx) options for industrial, automotive, and consumer applications.

ECP5 VIP Processor Board Connector Block Diagram


Partnerships, some of which are discussed above, are strategically important to Lattice; and for any business for that matter. A good partnership provides a business competitive edge, access to additional resources, supports customer-base growth, and enables access to new product and services. Our partners bring value to our customers which helps us mutually reach a new market and strengthen business for both.

A strategic partnership is always greater than the sum of its parts. Two heads are better than one and success comes when we work together.