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Lattice Diamond 3.9 - Improving IP Security, Power and Hardware Management

Lattice Diamond 3.9
Posted 04/25/2017 by Choon-Hoe Yeoh

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We kicked off 2017 with the release of Lattice Diamond 3.9, focusing on improving several areas for your FPGA designs, such as the IP RTL encryption productivity and power aware design flow, as well as increased ASC device support coverage.

Improved Collaboration

IP RTL encryption has been a critical part of the FPGA design flow, especially when IP reuse and external cross-organizational design collaborations are needed. In Lattice Diamond 3.9, we added Linux encryption platform support. This will help create a more streamlined flow for the users working on getting more computing capacity and throughput in the Linux environment. Additionally, we have added hierarchical viewing capability and Reveal logic analyzer support on the encrypted IP RTL, which will provide more diagnosis channels on the designs with encrypted IP RTL and therefore help to improve design closure productivity significantly.

Lower Power Consumption

Lattice Diamond 3.9 continues to embrace Lattice’s tradition of creating low power consuming products in an effort to improve power-aware design flow. We enhanced our power calculator with high order mathematical modeling equations and corresponding silicon characterization data, to provide much better silicon correlation and therefore speeding up the power design closure. This upgrade is available for our CrossLink FPGA product family and any other programmable devices released since Q3 2016. In power-sensitive designs, where it is important to turn off any power consuming elements in the design when not in use, the Lattice Diamond 3.9 update has added the ability to disable input buffer for unused or output-only I/Os in the MachXO2 and MachXO3 families.

Design Support for More Products

With this release, we have also expanded the support for ASC device family across several FPGA/CPLD device product lines. This continues to strengthen the flagship hardware management platform offering, where more FPGA/CPLD device families, such as MachXO2HE, MachXO3L and most of ECP5 and ECP5-5G products, can now be utilized to develop hardware management solutions based on the different needs of the customers.

We understand that software is a critical component of any design that utilizes FPGAs. As an industry leader of smart connectivity solutions, we always incorporate our insight into upcoming industry trends along with user feedback, whenever we work on an update to ensure our customers are set up for success.