Lattice Blog


Distributed Heterogeneous Processing Opens New Applications for FPGAs

Posted 12/20/2016 by Abdullah Raouf

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Increasingly lower cost sensors, the migration to higher performance I/O interfaces, and the demand for “always-on, always-aware” functionality all present new challenges for designers of battery-powered mobile devices. Engineers building everything from phones and drones to wearables and industrial equipment are facing the same problem. How do they process large amounts of data in shorter periods of time, while reducing system power to meet customers’ demand for longer battery runtimes?

Abandoning the traditional CPU-centric design methodology, designers are realizing they must take advantage of the diversity of processors and sensors in today’s systems to maximize energy efficiency while meeting ever-higher computational requirements. To do this, designers are migrating to Distributed Heterogeneous Processing (DHP) architectures.

What is Distributed Heterogeneous Processing (DHP)?

Rather than computing algorithms in the cloud, DHP meets the need for complex co-processing using local dissimilar processors. By performing repetitive number-crunching tasks on power-efficient FPGAs with built in Digital Signal Processors (DSPs), this new strategy reduces the computational load on the power hungry Applications Processor (AP), allowing longer sleep modes and extending battery life.

The adoption of DHP techniques offers further benefits. First and foremost, it opens the door for a wide variety of new FPGA applications and new generations of FPGAs that offer deeper memory resources, extensive computation capabilities and the ability to deliver these functions in a low power, highly compact footprint. Case in point is our new iCE40 UltraPlus devices, which offer 8X the memory and 2X the number of DSPs found on previous devices, while dissipating as little as 75 µA in static power mode. Let’s take a look at some possible use cases.

Sense and Detect Acceleration

One example of these new applications is the wake-up process in mobile devices. A growing number of battery-powered devices today feature an always-on sensor buffer to perform sense and detect acceleration while the AP is in sleep mode.  But to maximize power efficiency and stretch battery runtime, these mobile devices need to mask fake wake-up calls to keep the AP in sleep mode as long as possible.

Typically, these systems use a double tap or “shake-to-wake” function or fingerprint, gesture or eye scan techniques to wake up the AP. Oftentimes these systems employ a two-step process. First, the system determines if a wake-up action occurred. Second, it determines if the fingerprint, gesture or eye scan is accurate.

Until recently, designers have used a small FPGA seated between the sensors and the AP to detect when a wake-up action, such as the presentation of a fingerprint, occurred. Once the action was confirmed, the FPGA would wake up the AP to evaluate if the fingerprint was correct. With the larger memory and additional computational capabilities of the iCE40 UltraPlus FPGAs, designers can now perform both wake-up process functions simultaneously, allowing the AP to remain in sleep mode longer.

High Performance Audio Processing

Acoustic beamforming offers another potential new application for FPGAs. To support this functionality, applications designers need to deliver a high level of audio processing to isolate specific audio signals in noisy environments. But how does a system detect one person’s commands in a room where multiple people are talking?

Beamforming technology uses multiple microphone arrays to isolate a specific voice from undesirable noise. Some leading products on the market today employ beamforming technology and use multiple microphones to distinguish the user’s voice from other voices and background noise.  Yet, most APs on the market are only designed to support the use of two mics. To accomplish this task designers needed to operate 24 x 7 using up to 7 mics without draining the battery.

To accomplish such tasks, designers can connect the microphone array to an iCE40 UltraPlus FPGA and then have the FPGA interface with the acoustic processor. Multiply and accumulate (MAC) blocks on the FPGA would be used for PDM decimation and filtering, while the FPGA’s deep memory can support microphone delay lines. This approach also gives designers a new ability to customize their system using on-chip MACs as well as the ability to construct very flexible beamforming filters, noise cancelling systems, or equalization capabilities.

The iCE40 UltraPlus can enable a variety of solutions beyond those described above. To learn more, please check out the resources below: