The Lattice Semiconductor SubLVDS Image Sensor Receiver IP Core converts double data rate interface to pixel clock domain. The SubLVDS interface is primarily used in image sensors. The interface has one clock pair and more than one data pairs. The number of data pairs varies, depending on bandwidth requirement. SubLVDS is a source synchronous interface, the clock pair is running at the same rate as the data. This is not a 7:1 interface. SubLVDS has the clock center-aligned with the data.
Resource Utilization details are available in the IP Core User Guide.
Features
- Supports 4, 6, 8, 10, 12, 14, or 16 data lanes from an image sensor.
- Supports 10-bit (RAW10) or 12-bit (RAW12) pixel widths.
- Supports gearing of 8 and 16. The gearing 16 option is only for 4-lane configuration.
- Supports APB Interface for register access and AXI4-Stream Transmit Interface.
- Can generate XVS and XHS for image sensors operating in Passive mode.
