The Lattice I3C IP Core is designed to comply with the MIPI I3C specification. An I3C bus requires exactly one I3C device at a time functioning as an I3C Controller device. In I3C terms, this I3C Controller device is the active Controller at that time.
I3C Controller IP supports several communication formats, all sharing a two-wire interface: SDA bidirectional data line and SCL bidirectional clock. The Lattice I3C Controller supports the following modes:
- SDR mode
- HDR-DDR mode
Resource Utilization details are available in the IP Core User Guide.
Features
- Compatible with MIPI I3C Specification v1.1.1
- Two wire serial interface up to 12.5 MHz using Push-Pull
- Legacy I2C device coexist on the same bus (with some limitations)
- Dynamic Addressing while supporting Static Addressing for legacy I2C devices
- I2C-like SDR messaging
