The Lattice I3C IP Core is designed to comply with the MIPI I3C specification. Both Controller and Target versions of this IP Core are available.
The I3C Target listens to I3C bus for relevant I3C commands sent by the I3C Controller and responds accordingly. This includes all Broadcast Commands (CCC), and any Directed Commands (CCC) addressed specifically to that I3C Target Device and supported by that I3C Target Device. The I3C Target IP accepts commands from LMMI or from the optional APB/AHB-Lite interface. These commands are decoded into (1) configurations for the I3C Target that may be requested by the Controller and (2) I3C signals that the Target may transmit to the I3C bus.
Eases Sensor System Design Architectures - The MIPI I3C interface eases sensor system design architectures in mobile wireless products by providing a fast, low-cost, low-power, two-wire digital interface for sensors. I3C a single scalable, cost effective, power efficient protocol to solve issues with the high protocol overhead, power consumption, nonstandard protocol, separate lines for interrupt and the rest requirement.
Offers Greater Than 10x Speed Improvements - I3C offers greater than 10x speed improvements, more efficient bus power management, new communication Modes, and new Device roles, including an ability to change Device Roles over time
Supports Several Communication Formats - I3C Target IP supports several communication formats, all sharing a two-wire interface: SDA bidirectional data line and SCL input.