Lattice Propel Opens a World of Possibilities for Software Developers

Do you develop software for embedded systems? Are you interested in using RISC-V processors? Would you like to be able to quickly and easily create your own RISC-V device that’s customized to the needs of your application without having to know anything about hardware design? If you’ve answered “Yes” to any of these questions, I’m about to make you very happy indeed.

Things are evolving dramatically in embedded design space. Until relatively recently, computation-intensive tasks like security, analysis, artificial intelligence (AI), and machine learning (ML) were predominantly to be found in the Cloud. Now, such tasks are increasingly being deployed in devices at the Edge; that is, the boundary where the internet meets, and interfaces with, the real world.

Another trend is the rapidly increasing use of RISC-V processors, where RISC-V is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles that is made available under open-source licenses. As reported by Jeff Shepard in his RISC-V is Growing and Offers Stability, Scalability, and Security article on MicrocontrollerTips.com, “Semico Research has projected that 62.4 billion RISC-V CPU cores will be sold by 2025. While that’s only about six percent of the overall CPU core market, RISC-V is an emerging technology that most designers should follow and become increasingly familiar with.”

Also of interest is the increasing use of field-programmable gate arrays (FPGAs) in embedded systems. Certain data processing tasks, including many AI/ML algorithms, can benefit from parallel processing. Traditional microprocessors (MPUs) and microcontrollers (MCUs) are great when it comes to decision-making tasks, but they can be inefficient in terms of time and power consumption when it comes to implementing raw data processing algorithms. By comparison, the programmable fabric in FPGAs (Figure 1a) can be configured to implement hardware accelerator (HA) functions that perform data processing algorithms in a massively parallel fashion (Figure 1b), thereby providing fast performance with low latency while consuming relatively little power.

Figure 1. The combination of hardware accelerators and RISC-V processors is advantageous for a wide variety of applications, including embedded vision, security, and artificial intelligence.

In many cases, it is required to augment these hardware accelerators with a central processing unit (CPU) that can perform high-level decision-making and control functions. As opposed to a hard-core CPU that is implemented directly in the silicon, some of the FPGA’s programmable fabric can be used to implement a soft-core CPU along with an associated bus structure (address, data, control) and any required peripheral intellectual property (IP) functions (Figure 1c).

A general problem for software developers, until now, they have been intimidated by the thought of using traditional FPGA design tools and hardware description languages (HDLs). As a result, they have been at the mercy of hardware design engineers to configure and implement the RISC-V processor on the FPGA.

The solution is Lattice Propel™, which is a state-of-the-art standalone graphical user interface (GUI)-based design environment that allows any user (with or without FPGA expertise) to employ a drag-and-drop methodology to capture and configure a RISC-V processor-based design in minutes.

Figure 2. Propel allows software developers to achieve success in minutes, from simple “Hello World” type applications to complex embedded control and data processing systems.

In addition to drag-and-drop instantiation, the Propel Builder features automated pin-to-pin connections, wizard-guided configuration and parameterization, and correct-by-construction IP integration.

Propel also boasts a seamless software development environment in the form of a software development kit (SDK) that features an industry-standard integrated development environment (IDE) and toolchain. The SDK features software/hardware debugging capabilities along with software libraries and board support packages (BSPs) for Propel-defined systems.

The output from Propel is an RTL file in Verilog HDL that can be passed to the synthesis engine, which generates the configuration file to be loaded into the FPGA. This configuration file can be targeted at the Lattice MachXO3D™, Mach™-NX, CrossLink™-NX, and Certus™-NX FPGA families.

Now, software developers no longer need to wait for their hardware counterparts. Once they’ve configured the FPGA with their RISC-V design, they can run their RISC-V executable files on this FPGA-based RISC-V implementation as they would with any other RISC-V processor. The availability of Lattice Propel opens a world of possibilities for software developers.

For more information, visit the Propel Webpage and read the Propel Whitepaper.