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IP Core

Quad GbE Over SONET/SDH

Archived IP Core supporting ORCA FPGAs - For reference only.

IP Core

Quad SPI-3 to SPI-4 PHY Layer Bridge

Archived IP Core supporting ORCA FPGAs - For reference only.

IP Core

Quad SPI-3 to SPI-4 Link Layer Bridge

Archived IP Core supporting ORCA FPGAs - For reference only.

FAQ

CertusPro-NX PCIe: Does both Quad 0 and Quad 1 support hard IP block of PCIe link layer?

CertusPro-NX only supports the hard IP block PCIe link layer on Quad 0. For more information, refer to second paragraph of section '11.1. PCI Express Mode' on FPGA-TN-02245.

FAQ

CertusPro-NX SERDES: Should the unused channel/s on a SerDes Quad be powered?

Solution:The only requirement is to power-up the channel 1 of the used quad even if this channel is unused.The rest of the unused channel/s can be left floating or not connected. Refer to Section 13.5 of the CertusPro-NX SerDes/PCS User Guide (FPGA-TN-02245)Note section: Channel 1 of the used…

IP Core

QSPI Flash Controller IP Core

The QSPI Flash Controller IP allows communication with multiple external SPI flash devices using standard, extended dual/quad, dual, or quad SPI protocols.

FAQ

LatticeECP3: Why is the SERDES Quad C powered by VCCIB instead of supplying 1.2v, or 1.5v with passive filtering?

The SERDES Quad C of LatticeECP3 FPGA on the Video Protocol board is reserved for HDMI/DVI interface. The HDMI/DVI interface is using TMDS signaling which has a common mode voltage around 3V and a differential swing range of 400-600mV. In order for Lattice CML SERDES to receive HDMI/DVI, the…

FAQ

All Nexus Families: How are the commands and bitstream sent in the Nexus device via Quad (x4) Slave SPI?

See below on how to send the commands in Quad (x4) SSPI mode in comparison to Standard(x1) SSPI mode1.) See below comparison on how the commands are sent using Standard Slave SPI vs. Quad Slave SPI.In this example, the LSC_REFRESH (0x79) command was used.* In Standard Slave SPI, the…

FAQ

LatticeECP2/M: What is the difference between Quad Based Protocol Mode and Channel Based Protocol Mode?

When in Quad Based Protocol Mode, the four channels in the same quad will be configured to the same rate -- either full-data-rate mode(Reference Clock Multiplier set to 10X or 20X) or half-data-rate mode(Reference Clock Multiplier set to 10XH or 20XH).  In this case the Reference…

FAQ

LatticeECP2/M /LatticeECP3: How can I implement multiple protocols within a PCS quad (Protocol A RX, Protocol B, TX, etc) ?

For LatticeECP2M devices, all the four channels in a quad must be configured for the same protocol. In LatticeECP3 device family, multiple protocols within one quad of SERDES is supported. The standards are required to have the same reference clock frequency either at the full-rate or…

Webpage

Avant MPPHY Module

The MPPHY Module supports the most common high-speed SERDES protocols used for inter-chip connectivity.

Document

ORCA ORLI10G Quad 2.5Gbps, 10Gbps Quad 3.125Gbps, 12.5Gbps Line Interface FPSC Data Sheet

Data Sheet PDF 0.9MB

Document

PCN01A-08 Notification of Intent to Utilize an AQAS and an AQMS for Select Plastic Quad Flat Pack and Shrink Quad Flat Pack Devices

PCN & Design Advisories 1 PDF 139.6KB

FAQ

Why do I occasionally see invalid 8b10b characters at the PCS/SERDES QUAD RX FPGA FIFO interface even though the PCS link state machine shows correct status?

When the Lattice SERDES/PCS QUAD is powered up, the PCS recovered clocks are unstable until the RX CDR locks fully to the incoming data.During the time the RX clocks are unstable, the pointers on the PCS  RX FPGA  interface FIFO (RX FIFO) can reach invalid values.When the CDR finally locks ,…

FAQ

In TN1176, it says VCCA of unused quad should be powered up. What is the reason to power up unused quad? Can I save power by leave the VCCA floating?

The required power, when the quad is in powered down mode(unused quad is powered down by default internally) but VCCA is poweredup,  draws very little current. That is hardly a problem for the users. There is specific reason we want the VCCA pins to be powered up. Without powering them…

FAQ

LatticeECP3: If I am not using one of the SERDES/PCS quads of my device, are there any special considerations as far as layout is concerned?If I don't want to use a quad of SERDES/PCS, w

If you are not using SERDES/PCS, you need to do the following steps:1. Connect power: VCCA and ground VSSA; 2. Let other power domains (VCCIB and VCCOB) floating; 3. Let the other signal pins such as ;HDINP/N, HDOUTP/N and REF-CLKP/N floating. all the unused channel outputs are tri-stated with…

Webpage

ECP5 / ECP5-5G

With a focus on compact, high volume applications, Lattice optimized ECP5 for low cost, small form factor and low power consumption. These characteristics make ECP5 ideal for delivering programmable connectivity to complement ASICs and ASSPs.

IP Core

Octal SPI Controller IP Core

​​Octal SPI Controller IP Core supports various types of SPI protocols & provides a flexible Transaction Layer Interface to the PCI Express Bus.​

Document

Quad SPI-3 to SPI-4 PHY Layer Bridge User's Guide

User Manual IPUG24 02.0 PDF 301.8KB

Document

Quad SPI-3 to SPI-4 Link Layer Bridge User's Guide

User Manual PDF 189.4KB