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CMOS to MIPI D-PHY Interface Bridge Soft IP User Guide

CMOS to MIPI D-PHY Interface Bridge Soft IP Supporting MIPI CSI-2 and MIPI DSI for Image Sensor Interface and Displays User Guide FPGA-IPUG-02007-1.4 April 2019 CMOS to MIPI D-PHY Interface Bridge Soft IP Supporting MIPI CSI-2 and MIPI DSI for Image Sensor Interface and…

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DSP Function Usage Guide for ICE40 Devices

DSP Function Usage Guide for iCE40 Devices Technical Note FPGA-TN-02007-1.2 October 2020 DSP Function Usage Guide for iCE40 Devices Technical Note FPGA-TN-02007-1.2 October 2020 DSP Function Usage Guide for iCE40 Devices Technical Note © 2016-2020 Lattice Semiconductor Corp.

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iCE40 UltraPlus MDP User Guide

The specifications and information herein are subject to change without notice. 4 FPGA-EB-02007-1.2 1. Introduction Thank you for choosing the Lattice iCE40 UltraPlus™ Mobile Development Platform (MDP) Board.

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LatticeMico32 Tri-Speed Ethernet MAC Gigabit Demo for the ECP5 and ECP5-5G Versa Development Board - User Guide

LatticeMico32 Tri-Speed Ethernet MAC Gigabit Demo for the ECP5/ECP5-5G Versa Development Kit User Guide FPGA-UG-02007-1.1 August 2022 LatticeMico32 Tri-Speed Ethernet MAC Gigabit Demo for the ECP5/ECP5-5G Versa Development Kit User Guide FPGA-UG-02007-1.1 August 2022…

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Aldec Active-HDL Lattice Edition Floating License Setup (Windows/Linux)

Aldec Active-HDL Lattice Edition Floating License Setup (Windows/Linux) Application Note FPGA-AN-02007-1.2 August 2019 Aldec Active-HDL Lattice Edition Floating License Setup (Windows/Linux) Application Note FPGA-AN-02007-1.2 August 2019 Aldec Active-HDL Lattice Edition Floating…

FAQ

PCIe for Nexus FPGAs: How to access PCIe peripherals using AHB-lite interface?

Solution:DMA support must be enabled to access the PCIe endpoint through AHB-lite.The DMA (Direct Memory Access) support has an option to enable efficient data transfer when the device acts as an initiator or a master.For more information, refer to DMA Support section in the FPGA-IPUG-02091 (for…

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CrossLink Family Data Sheet

Data Sheet, Key Documents FPGA-DS-02007 2.2 PDF 1.1MB

FAQ

In D-PHY to CMOS V1.3 for crosslink application, why does v_sync signal not normal compared to the datasheet? When the data valid, V_sync have the low level and when v_sync is high, it have no h_sync.

Waveform found in Fig 2.5 of the documentation has to be updated. For reference on the correct waveform, please refer to byte-to-pixel converter IP, under FPGA-IPUG-02027 to be specific, it is under Fig 2.2.

FAQ

PCIe for Nexus FPGA: How to write the Link Layer Configuration Space Registers on PCIe device?

Solution:1.      Defining the usr_lmmi_offset_i [16:2]a.      usr_lmmi_offset_i [16] == selects between Link Layer or PHY register accessb.      usr_lmmi_offset [15:2] == refer to FPGA-IPUG-02126 \u00E0 word aligned offset of base + offset address2.      Write \u201C1'b0\u201D on usr_lmmi_offset_i…

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Avant PLL Module User Guide - Lattice Radiant Software

Lattice Avant PLL Module IP Version: 2.6.0 User Guide FPGA-IPUG-02220-1.5 April 2025 Lattice Avant PLL Module IP Version: 2.6.0 User Guide FPGA-IPUG-02220-1.5 April 2025 Lattice Avant PLL Module User Guide © 2025 Lattice Semiconductor Corp.

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PLL Module User Guide - Lattice Radiant Software

PLL Module User Guide FPGA-IPUG-02063-2.0 October 2024 PLL Module User Guide FPGA-IPUG-02063-2.0 October 2024 PLL Module User Guide © 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at…

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UART 16550 IP Core User Guide

UART 16550 IP Core - Lattice Radiant Software User Guide FPGA-IPUG-02035-1.3 December 2019 UART 16550 IP Core - Lattice Radiant Software User Guide FPGA-IPUG-02035-1.3 December 2019 UART 16550 IP Core - Lattice Radiant Software User Guide © 2018-2019 Lattice Semiconductor…

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MDIO Leader IP Core - User Guide

MDIO Leader IP IP Version: v1.3.0 User Guide FPGA-IPUG-02223-1.3 December 2025 MDIO Leader IP IP Version: v1.3.0 User Guide FPGA-IPUG-02223-1.3 December 2025 MDIO Leader IP User Guide © 2025 Lattice Semiconductor Corp.

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Compact CNN Accelerator IP User Guide

Compact CNN Accelerator IP Core User Guide FPGA-IPUG-02038-1.7 December 2020 Compact CNN Accelerator IP Core User Guide FPGA-IPUG-02038-1.7 December 2020 Compact CNN Accelerator IP Core User Guide © 2018-2020 Lattice Semiconductor Corp.

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Gamma Corrector IP Core - User Guide

Gamma Corrector IP IP Version: 1.7.1 User Guide FPGA-IPUG-02122-1.6 December 2025 Gamma Corrector IP IP Version: 1.7.1 User Guide FPGA-IPUG-02122-1.6 December 2025 Gamma Corrector IP User Guide © 2025 Lattice Semiconductor Corp.

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Lattice Sentry QSPI Streamer - User's Guide

Lattice Sentry QSPI Controller Streamer IP – Lattice Propel Builder IP Version: 1.2.0 User Guide FPGA-IPUG-02109-1.1 December 2025 Lattice Sentry QSPI Controller Streamer IP – Lattice Propel Builder IP Version: 1.2.0 User Guide FPGA-IPUG-02109-1.1 December 2025…

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Lattice Sentry I2C Monitor IP Core - User Guide

Lattice Sentry I2C Monitor IP IP Version: v1.1.0 User Guide FPGA-IPUG-02108-1.1 December 2025 Lattice Sentry I2C Monitor IP IP Version: v1.1.0 User Guide FPGA-IPUG-02108-1.1 December 2025 Lattice Sentry I2C Monitor IP User Guide © 2025 Lattice Semiconductor Corp.

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ADC Core Module User Guide - Lattice Radiant Software

ADC Core Module User Guide FPGA-IPUG-02168-1.5 January 2025 ADC Core Module User Guide FPGA-IPUG-02168-1.5 January 2025 ADC Core Module User Guide © 2025 Lattice Semiconductor Corp.

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Nexus DDR 7:1 Module User Guide - Lattice Radiant Software

DDR 7:1 Module User Guide FPGA-IPUG-02058-1.8 June 2024 DDR 7:1 Module User Guide FPGA-IPUG-02058-1.8 June 2024 DDR 7:1 Module User Guide © 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at…

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SubLVDS Image Sensor Receiver IP Core - User Guide

SubLVDS Image Sensor Receiver IP IP Version: 1.7.1 User Guide FPGA-IPUG-02093-2.2 December 2025 SubLVDS Image Sensor Receiver IP IP Version: 1.7.1 User Guide FPGA-IPUG-02093-2.2 December 2025 SubLVDS Image Sensor Receiver IP User Guide © 2025 Lattice Semiconductor Corp.