Article Details

ID: 5460
Case Type: faq
Category: Lattice IP/Reference Design
Related To:
Family: CrossLink

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In D-PHY to CMOS V1.3 for crosslink application, why does v_sync signal not normal compared to the datasheet? When the data valid, V_sync have the low level and when v_sync is high, it have no h_sync.

Waveform found in Fig 2.5 of the documentation has to be updated. For reference on the correct waveform, please refer to byte-to-pixel converter IP, under FPGA-IPUG-02027 to be specific, it is under Fig 2.2.
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