Single Wire Aggregation Demo / Development Board

PCB congestion relief using FPGAs for signal aggregation and transmission over single wire

System Design Challenges – Connectors are the single highest contributor to system reliability. They also consume valuable PCB and system space, which is especially critical in hinged applications such as in notebooks. Single Wire Aggregation allows you to reduce your connector and cable size while increasing your reliability.

Single Wire Demonstration – Two boards are provided to demonstrate the complete working design in a stand-alone configuration.

Single Wire Prototyping – Two boards are provided can be re-configured to interface to a prototype system to demonstrate the proof of concept in-system.

Features

  • No FPGA tools knowledge necessary
  • Customizable via available Reference Design
  • Up to 7 channels can be aggregated
  • Each channel can be either I2C, I2S or GPIO
  • Board set can be configured as a stand-alone demo or in-system proof of concept

Jump to

Videos

How to Setup SWA DemoExpand Image

How to Setup SWA Demo

How to Run SWA DemoExpand Image

How to Run SWA Demo

SWA Board OverviewExpand Image

SWA Board Overview

Block Diagrams

Single Wire Aggregation Demo/Dev Board – Block Diagram

  • Configurable for demonstration or prototyping
  • 12 Total Test Switches Available
  • Jumpers enable connection of RD to Data Generator/Verifier OR customer’s prototype
  • 12 output LEDs Available

Configuration #1 (I2Sx2_I2CSx1_I2CMx1_GPIOx8)

  • Two directional I2S channels (32 bits data width, 36 kHz audio sampling)
  • One I2C Controller to Peripheral channel
  • One I2C Peripheral to Controller channel
  • 6 bits bidirectional GPIO channel
  • 2 bits bidirectional GPIO channel

Configuration #2 (I2CMx6_GPIOx6)

  • Six I2C Controller to Peripheral channels (at 400kHZ SCL clock)
  • 6 bits bidirectional GPIO channel

Configuration #3 (I2CMx1_GPIOx12)

  • ONE I2C Controller to Peripheral Channel (at 1MHz SCL clock)
  • 12 bits bidirectional GPIO Channel

Configuration #4 (I2CMx3_I2CSx2_GPIOx15)

  • Three I2C Controller to Peripheral Channels
  • Two I2C Peripheral to Controller Channels
  • 15 bits Controller to Peripheral GPIO channel

Configuration #5 (I2Sx1_I2CMx1_I2CSx1_GPIOx8)

  • One directional I2S channels (32 bits data width, up to 48 kHz audio sampling)
  • One I2C Controller to Peripheral channel
  • One I2C Peripheral to Controller channel
  • 6 bits bidirectional GPIO channel
  • 2 bits bidirectional GPIO channel

Board Photos

Side View

Ordering Information

  • Ordering Part Number: iCE40UP5K-SWA-EVN
  • Click here to find an authorized Lattice distributor near you

Documentation

Quick Reference
Technical Resources
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
Single Wire Aggregation
FPGA-UG-02117 1.0 9/9/2020 PDF 5.2 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
iCE40 Single Wire Aggregation Board V2.0 Schematic
1.0 9/9/2020 PDF 1.1 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Product Selector Guide
I0211 27.0 9/17/2020 PDF 8.9 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
FPGA-Based Single Wire Aggregation (SWA) for FPGA and Non-FPGA Designers
WP0026 1.0 9/16/2020 PDF 845.1 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
iCE40 Single Wire Aggregation Gerber X2
1.0 9/10/2020 ZIP 1.2 MB

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Custom Design Requests

Custom Designs

Click here to request a quick-turn custom Single Wire Aggregation via our technical support system.

Please file a technical support request here.

File Under:

  • Case Type: Reference Design
  • Case Category: Single WIre Aggregation Customization Request

Support

Quality & Reliability

Reference Material to Help Answer Your Questions

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