The Lattice Semiconductor USB 2.0/3.2 intellectual property (IP) core provides a solution to interface with the USB host. The design is implemented using Verilog HDL. The IP core is targeted for Lattice CrossLinkU™-NX FPGAs. The IP core is implemented using the Lattice Radiant™ software integrated with the Synopsys® Synplify Pro® synthesis tool.
The Lattice USB 2.0/3.2 IP core supports the USB-IF compliant USB standard.
Resource Utilization details are available in the Reference Design User Guide.
Features
- Supports High Speed and Full Speed USB 2.0 specification and Super Speed USB 3.2 specification
- Supports high-speed, high-bandwidth isochronous transactions
- Supports two control endpoints at EP0/1 (1 IN 1 OUT) and eight individually reconfigurable logical endpoints. Each logical endpoint reflect two physical endpoints, one IN and one OUT endpoint.
- Includes an example design as a reference usage model
