The Lattice Semiconductor 10G Ethernet (GbE) IP core supports the ability to transmit and receive data between a host processor and an Ethernet network. The 10GbE IP core consists of the 10-Gigabit Media Independent Interface (XGMII), which connects media access controllers (MACs) and Physical Layer devices (PHYs). The main function of the 10GbE MAC is to ensure that the media access rules specified in the 802.3 IEEE standards are met while transmitting a frame of data over an Ethernet.
IP Options:
CertusPro™-NX: MAC only, PHY only, MAC + PHY + 1588, and MAC + PHY
Avant™-G, Avant™-X, and Certus-N2: MAC only, PHY only, MAC + PHY, and ANLT
Resource Utilization details are available in the IP Core User Guide
Features
MAC
- Compliant to the IEEE 802.3-2012 standard
- Supports standard 10 Gbps Ethernet link layer data rate
- 64-bit wide internal datapath operating at 156.25 MHz
- AXI4-Stream interface on the client’s transmit and receive interfaces
- Supports deficit idle count (DIC)
PHY
- Designed to the IEEE 802.3-2012 10GBASE-R specification
- 64b/66b encoding and decoding
- XGMII interface: 64-bit, 156.25 MHz
- TX phase FIFO and RX clock compensation FIFO
MAC + PHY + 1588 (CertusPro-NX)
- Timestamping support as specified in the IEEE 1588v2 (2-step mode)
