Emulated LVDS will have maximum data rate near the device FMAX_IO frequency value if:
- the IOs are complimentary LVCMOS outputs (or have low timing skew)
- the IOs have similar rise and fall times
- the emulated LVDS output resistor network is placed physically next to the device output IO pins
- the PCB traces from the resistor network are differentially coupled, 50 ohm per side
- the signal traces are over a solid GND plane between the device and LVDS receiver
- the output IOs are set to fast slew setting
- you minimize the PCB trace lengths, connectors, and cables between the device and receiver