What can I do to maximize the emulated LVDS data rate?SupportArticlePage6d001106-4ef5-440d-8338-c8cbedbe7bd2FAQ/Support/AnswerDatabase/8/4/843https://edge.sitecorecloud.io/latticesemi9e32-latticesemi06bb-prod9ecc-d341/media/Project/Lattice/LatticeSemi/Images/SearchThumbnails/FAQ.png?sc_lang=enEmulated LVDS will have maximum data rate near the device FMAX_IO frequency value if: the IOs are complimentary LVCMOS outputs (or have low timing skew) the IOs have similar rise and fall times the emulated LVDS output resistor network is placed physically next to the device output IO pins the PCB traces from the resistor network are differentially coupled, 50 ohm per side the signal traces are over a solid GND plane between the device and LVDS receiver the output IOs are set to fast slew setting you minimize the PCB trace lengths, connectors, and cables between the device and receiver
