DDR SDRAM Controller


Newsletter Subscription

Reference Design LogoThe DDR SDRAM uses double data rate architecture to achieve high-speed data transfers. DDR SDRAM ( referred to as DDR) transfers data on both the rising and falling edge of the clock. This reference design provides an implementation of the DDR memory controller implemented in Lattice ORCA Series 4 FPGA device. This DDR controller is typically implemented in a system between the DDR and the bus master. Figure 1 shows the relationship of the controller between the bus master and the DDR. The bus master could be either a microprocessor like Intel's i960 or a user's proprietary module interface. For illustration purpose, the Micron's 4M x 8 x 4Banks DDR SDRAM is chosen for this design. The design was verified using Micron SDRAM simulation model.

Jump to

Block Diagram

DDR SDRAM Controller

Perforamance and Size

Language Max. Freq. I/O PFU Register Device*
Verilog 147MHz (w/PLL) 80/405 50/624 249 OR4E02-2

* May work in other devices as well.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.

Documentation

Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
DDR SDRAM Controller - Source Code
RD1020 4/1/2004 ZIP 18.7 KB
DDR SDRAM Controller - Documentation
RD1020 4/1/2004 ZIP 18.7 KB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

ABOUT LATTICE

SALES

SUPPORT

FOLLOW