PCI to NOR Flash Interface

Related Products

LatticeReferenceDesign-LogoThis reference design brings the capability and the performance of the popular PCI Local Bus to the NOR-based Flash. It provides an interface between the CPU with PCI initiator interface and a NOR-type Flash memory by translating the PCI commands into appropriate signals to control the read/write of the NOR Flash. The basic knowledge of PCI specification is necessary to understand the design.

Jump to

Block Diagram

Performance and Size

Tested Devices* Performance I/O Pins Design Size Revision
LCMXO2280C-3FT256C 33 MHz 113 288 LUTs 1.1
LFXP2-5E-5FT256C 33 MHz 113 310 LUTs 1.1

* May work in other devices as well.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.

Documentation

Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
PCI to NOR Flash Interface
RD1050 1.1 3/10/2010 PDF 367.9 KB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

Like most websites, we use cookies and similar technologies to enhance your user experience. We also allow third parties to place cookies on our website. By continuing to use this website you consent to the use of cookies as described in our Cookie Policy.

About Us

Sales

Support
 
 
 
 
 
 
Lattice QR code