DDR SDRAM Controller - Non-Pipelined


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This version of the Lattice DDR SDRAM Controller does not have pipelining, and is significantly smaller than the pipelined version. DDR (Double Data Rate) SDRAM was introduced as a replacement for SDRAM memory running at bus speeds over 75MHz. DDR SDRAM is similar in function to the regular SDRAM but doubles the bandwidth of the memory by transferring data twice per cycle on both edges of the clock signal, implementing burst mode data transfer.

The DDR SDRAM Controller is a parameterized core giving users the flexibility for modifying data widths, burst transfer rates and CAS latency settings in a design. In addition, the DDR core supports intelligent bank management, which is done by maintaining a database of "all banks activated" and the "rows activated" in each bank. With this information, the DDR SDRAM Controller decides if an active or pre-charge command is needed. This effectively reduces the latency of read/write commands issued to the DDR SDRAM.

Features

  • Performance of Greater than 133MHz (266 DDR)
  • Interfaces to JEDEC Standard DDR SDRAMs
  • Supports DDR SDRAM Data Widths of 16, 32 and 64 bits
  • Supports up to 8 External Memory Banks
  • Programmable Burst Lengths of 2, 4, or 8
  • Programmable CAS Latency of 1.5, 2.0, 2.5 or 3.0
  • Byte-level Writing Supported
  • Supports Power-down and Self Refresh Modes
  • Automatic Initialization
  • Automatic Refresh During Normal and Power-down Modes
  • Timing and Settings Parameters Implemented as Programmable Registers
  • Complete Synchronous Implementation

Jump to

Block Diagram

DDR SDRAM Controller - Non-Pipelined Block Diagram

Performance and Size

Performance and Utilization for ORCA41
Parameter File Core Configuration ORCA4
PFUs2		 LUTs Registers Dist.
RAM3		 fMAX
(MHz)		 External
Pins		 sysMEM™
EBRs
ddrct_np_o4_1_008.lpc Generic User I/F
(non-pipelined)		 283 703 1044 3 133 239 N/A

1 Performance and utilization characteristics are generated using an OR4E023BM416-DB in Lattice’s ispLEVER v.3.1 software. When using this IP core in a different density, package, speed, or grade within in the ORCA 4 family, performance may vary.
2 PFU is a standard logic block of some Lattice devices. For more information, check the data sheet of the device.3 Dist. RAM = distributed memory

Performance and Utilization for LatticeECP and LatticeEC FPGAs1
Parameter File SLICEs LUTs Registers I/Os sysMEMTM EBRs fMAX (MHz)
ddrct_np_e2_3_005.lpc 918 805 1369 229 0 200 MHz (400 DDR)

1 Performance and utilization characteristics are generated using LFEC20E-5F672C in Lattice's ispLEVER v.5.0 software. When using this IP core in a different density, speed, or grade within the LatticeECP/EC family, performance may vary.

Performance and Utilization for LatticeXP1
Parameter File SLICEs LUTs Registers I/Os sysMEMTM EBRs fMAX (MHz)
ddrct_np_xm_3_005.lpc 857 807 1237 229 0 166 MHz (333 DDR)

1 Performance and utilization characteristics are generated using LFXP10E-5F388C in Lattice's ispLEVER v5.0 software. When using this IP core in a different density, speed, or grade within the LatticeXP family, performance may vary.

Ordering Information

  • Ordering Part Number For ORCA 4: DDRCT-NP-O4-N1
  • Ordering Part Number For LatticeECP/EC: DDRCT-NP-E2-N3
  • Ordering Part Number For LatticeXP: DDRCT-NP-XM-N3

To find out how to purchase the 32 Bit PCI Target IP Core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
Downloads
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Board Timing Guidelines for the DDR SDRAM Controller IP Core
TN1071 1.1 9/6/2012 PDF 945.5 KB
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Board Timing Guidelines for the DDR SDRAM Controller IP Core
TN1071 1.1 9/6/2012 PDF 945.5 KB
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DDR SDRAM Controller - Non-Pipelined User Guide
12/1/2004 PDF 971.8 KB
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IP Module Evaluation Tutorial
8/1/2004 PDF 216.1 KB
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Evaluation Package for DDR SDRAM Controller - Non-Pipelined for ORCA 4
2/1/2004 ZIP 1.1 MB
Evaluation Package for DDR SDRAM Controller - Non-Pipelined for LatticeECP/EC
8/1/2005 ZIP 580.1 KB
Evaluation Package for DDR SDRAM Controller - Non-Pipelined for LatticeXP
5/1/2005 ZIP 650.6 KB

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