The HyperRAM Controller IP enables Lattice Nexus™ family devices to interface seamlessly with HyperRAM memories using the high performance HyperBus™ protocol. Designed in accordance with the HyperRAM 2.0 specification, the controller supports operation at up to 200 MHz, delivering throughput of up to 400 Mbps.
The controller provides two industry standard AXI interfaces—one dedicated to memory transactions and another for register configuration—offering a clean, flexible integration path for system designers. Its PHY implementation uses ODDRX1/IDDRX1 resources to ensure efficient operation and straightforward portability across the Nexus device family.