SPI Flash Controller with Wear Leveling

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Reference Design LogoFlash memory has been widely used in embedded systems to support various functions in products like consumer electronics. How to effectively manage Flash memory and extend the service cycles of a Flash memory has become the challenge faced by designers.

The maximum number of erase cycles for each sector or block of Flash memory is close to 100,000. For most applications, a master device often accesses and updates a few specific sectors. These sectors can wear out in a short period of time while the rest of the sectors are still valid for applications. Such behavior significantly reduces the lifetime of Flash memory and impacts overall product cost. Wear leveling is a technique to extend the service cycles of Flash memory by averaging the number of accesses to each sector. As a result, the number of erase cycles is distributed among all the sectors, thus extending the life of each sector of the Flash memory.

This reference design implements the wear leveling control of data storage for SPI Flash memory. The CPU stores the number of erases, logic-map-physical table, and the valid page pointers into Embedded Block RAM (EBR) or User Flash Memory (UFM) to keep track of the SPI Flash memory usage. A WISHBONE bus is used to interface between the master device and the wear leveling controller.


  • Configurable registers for command and data transfer
  • Manages number of erases for each sector
  • Manages logic-map-physical tables for the Flash memory
  • Provides valid page pointers
  • Supports SPI interface
  • WISHBONE compliant

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Block Diagram

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Performance and Size

Tested Devices* Language Performance I/O Pins Design Size Architecture Resources Revision
LCMXO2-1200HC-5TG100CES Verilog >24 MHz 37 359 LUTs 7 EBRs 1.0

* May work in other devices as well.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.


Technical Resources
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SPI Flash Controller with Wear Leveling
FPGA-RD-02101 1.1 1/29/2021 PDF 1 MB
SPI Flash Controller with Wear Leveling - Source code
RD1102 1.0 11/8/2010 ZIP 952.2 KB

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