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ID: 735
Case Type: faq
Category: Implementation
Related To: Synthesis
Family: All CPLD

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How can I make Synplify infer registers instead of RAM?

There might be situations where you have written Verilog or VHDL code which infers a memory. However the design tools are implementing this as distributed RAM, which can't be initialized or preset to zero. This can be a problem if you want to preset your memory.

The Synplify compiler (part of the Lattice ispLEVER and Diamond tools) infers the RAM type based on memory inferring code. By default, Synplify infers memory as distributed RAM (or Block RAM if available). In order to change the way Synplify infers this memory you must set an attribute on your code:

VHDL example:

attribute syn_ramstyle : string;
attribute syn_ramstyle of mem0_s, mem1_s, mem2_s, mem3_s : signal is "registers" ;

Verilog example:

reg [7:0] mem0_s[31:0] /* synthesis syn_ramstyle = "registers" */;

This will infer your memory as registers and not distributed RAM, allowing you to pre-set your memory. Be aware memory as registers is often not as resource efficient as using distributed or Block RAM resources.

There are three options to infer memory through this attribute:

registers - causes an inferred RAM to be mapped to registers (flip-flops and logic) rather than the technology-specific RAM resources.
distributed - causes the RAM to be implemented using the distributed RAM or PFU resources.
block_ram - causes the RAM to be implemented using the dedicated RAM resources.

If your RAM resources are limited, for whatever reason, you can map additional RAMs to registers instead of the dedicated or distributed RAM resources using this attribute.

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