Description:
Lattice Diamond software does not use any pre-synthesis constraint file (SDC/LDC/FDC).
Solution:
There is a workaround to compensate for the limitation.
Once the user has created any pre-synthesis constraint file, synthesize the design (for LSE) or synthesis + translate (for Synplify Pro). After that, the tool will generate an LPF file based on the SDC/LDC/FDC.
Since Diamond supported only LPF, the user has to copy the content of the generated LPF from the pre-synthesis constraint to the active LPF file.
The generated LPF file is located in the <project_name>/<implementation> folder.
Sample LDC constraint:
create_clock -period 20.000000 -name clk50 [ get_ports { CLK_IN_50MHz } ]
create_clock -period 20.000000 -name clk48 [ get_ports { CLK_IN_48MHz } ]
create_generated_clock -multiply_by 1 -source [ get_ports { CLK_IN_48MHz } ] -master_clock [ get_clocks { clk48 } ] -name intclk48 [ get_nets { Clock_48MHz } ]
create_generated_clock -divide_by 2 -source [ get_ports { CLK_IN_50MHz } ] -master_clock [ get_clocks { clk50 } ] -name intclk25 [ get_nets { Clock_25MHz } ]
create_generated_clock -multiply_by 2 -source [ get_ports { CLK_IN_50MHz } ] -master_clock [ get_clocks { clk50 } ] -name intclk100 [ get_nets { Clock_100MHz_90Deg } ]
create_generated_clock -multiply_by 1 -source [ get_ports { CLK_IN_50MHz } ] -master_clock [ get_clocks { clk50 } ] -name intclk50 [ get_nets { PHY_CLK } ]
Generated LPF based from LDC:
PERIOD PORT "CLK_IN_50MHz" 20.000 ns HIGH 10.000 ns ;
PERIOD PORT "CLK_IN_48MHz" 20.000 ns HIGH 10.000 ns ;
PERIOD NET "Clock_48MHz" 20.000 ns HIGH 10.000 ns ;
PERIOD NET "MII_CH2_RxCLK_c" 40.000 ns HIGH 20.000 ns ;
PERIOD NET "ClockResetGen/Clock_100MHz_90Deg" 10.000 ns HIGH 5.000 ns ;
PERIOD PORT "PHY_CLK" 20.000 ns HIGH 10.000 ns ;
CLKSKEWDIFF CLKPORT "CLK_IN_50MHz" CLKPORT "CLK_IN_48MHz" 0.000 ns ;
CLKSKEWDIFF CLKPORT "CLK_IN_50MHz" CLKPORT "PHY_CLK" 0.000 ns ;
CLKSKEWDIFF CLKPORT "CLK_IN_48MHz" CLKPORT "PHY_CLK" 0.000 ns ;