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ID: 566
Case Type: faq
Category: Architecture
Related To: Power
Family: All CPLD

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Can reducing IO voltage levels save power?

Yes, reducing the IO standard voltage level eg:- LVCMOS33 to LVCMOS25 is a good way to save dynamic power. The saving you will see will be in the mA range. The option to change the IO standard voltage level should be done early in the design stage so devices with matching IO standards can be selected.