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ID: 4041
Case Type: faq
Category: Architecture
Related To: PLL/DLL/Clock Routing
Family: MachXO2

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How to calculate CPHASE, FPHASE, ICP_CURRENT, LPF_RESISTOR values for PLL configuration in MachXO2?

TN1199, Appendix D, describes the operation to control the PLL dynamically via wishbone.


For accessing this link, select MachXO2 in Product on our Website and then go to Application Notes.

The description about the PLL attributes can be checked from the following Lattice Diamond online help link,


1) The "ICP_CURRENT" and "LPF_RESISTOR" attributes are used to vary the bandwidth of the loop filter of the PLL. Referring to TN1199, Table 13-17, the "MC1_IPROG[4:0]" and "MC1_RPROG[6:0]" registers are used to set the ICP current and LPF capacitor values, respectively. But these registers are not user accessible and hence it can't be controlled dynamically via wishbone. For the selected Pll clock outputs, these values are calculated automatically by the IPexpress tool.

2) The "*_ CPHASE" and "*_FPHASE" are used for phase adjustments of the PLL clock outputs. Referring to TN1199, Table 13-17, the "MC1_DEL*[6:0]" (i.e reg 2,3,4 & 4) and "MC1_PHI*[2:0]" (i.e. reg A & B) registers are used to set the phase shift value. For the selected PLL clock outputs, these values are calculated automatically by the IPexpress tool.
If the pll output clock phase needs to be changed dynamically, then these registers can be written to perform phase shift. These registers are user accessible.

For "*_FPHASE", set the "MC1_PHI*[2:0]" register:
Default value of MC1_PHI*[2:0] is "000" which is the VCO_PHASE_0 (Default)
Now, changing the value of MC1_PHI*[2:0] represents 45 degree shift of the VCO as below. This can be done dynamically.

001 VCO_PHASE_45

010 VCO_PHASE_90

011 VCO_PHASE_135

100 VCO_PHASE_180

101 VCO_PHASE_225

110 VCO_PHASE_270

111 VCO_PHASE_315

For "*_ CPHASE" , set the"MC1_DEL*[6:0]" register:
CLK_* section Delay value for coarse phase adjustments. For zero delay this value should be equal to the value of MC1_DIVA[6:0].

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