Description:
Nets and wires that are not driven will be optimized by the tool to reduce the number of resources during synthesis. In order to place it even if the nets and wires are not driven by any load, attributes syn_keep/noclio, and syn_preserve/syn_force_pads are added in the RTL.
Solution:
To prevent the synthesizer from optimizing away unused I/Os in your design, use the attributes of Synplify Pro.
See the example code below.
Example:
1.\tLattice Synthesis Engine (LSE)
\ta.\tVerilog
\t\t//************************************************************************************
\t\t\tmodule Dummy_IOs (dummy_in, dummy_out);
\t\t\tinput \t[1:0] dummy_in;
\t\t\toutput\t[1:0] dummy_out;
\t\t\t
\t\t\twire [1:0] dummy_signal_in\t/* synthesis syn_keep=1 */ /* synthesis NOCLIP="on"*/;
\t\t\twire [1:0] dummy_signal_out\t/* synthesis syn_keep=1 */;
\t\t\t
\t\t\tassign dummy_signal_in = dummy_in; \t//dummy statement for preserving inputs
\t\t\tassign dummy_out = dummy_signal_out;\t//dummy statement for preserving outputs
\t\t\t
\t\t\tendmodule
\t\t//************************************************************************************
\tb.\tVHDL
\t\t--************************************************************************************
\t\t\tlibrary ieee;
\t\t\tuse ieee.std_logic_1164.all;
\t\t\t
\t\t\tentity Dummy_IOs is
\t\t\t
\t\t\tport\t
\t\t\t\t(
\t\t\t\t\tdummy_in : in \tstd_logic_vector (1 downto 0);
\t\t\t\t\tdummy_out : out std_logic_vector (1 downto 0)
\t\t\t\t);
\t\t\t
\t\t\tend Dummy_IOs;
\t\t\t
\t\t\tarchitecture rtl of Dummy_IOs is
\t\t\t
\t\t\tsignal dummy_signal_in \t: std_logic_vector(1 downto 0);
\t\t\tsignal dummy_signal_out : std_logic_vector(1 downto 0);
\t\t\t
\t\t\t
\t\t\tattribute syn_keep : boolean;
\t\t\tattribute noclip : string;
\t\t\t
\t\t\tattribute noclip \tof dummy_signal_in : signal is "on";
\t\t\tattribute syn_keep \tof dummy_signal_in \t: signal is true;
\t\t\tattribute syn_keep \tof dummy_signal_out : signal is true;
\t\t\t
\t\t\t
\t\t\tbegin
\t\t\t
\t\t\t\tdummy_signal_in <= dummy_in; \t-- dummy statement for preserving inputs
\t\t\t\tdummy_out <= dummy_signal_out; \t-- dummy statement for preserving outputs
\t\t\t
\t\t\tend rtl;
\t\t--************************************************************************************
2.\tSynplify Pro
\ta.\tVerilog
\t\t//************************************************************************************
\t\t\tmodule Dummy_IOs (dummy_pins) /* synthesis syn_force_pads=1 syn_noprune=1*/;
\t\t\tinout \t[3:0] dummy_pins;
\t\t\twire dummy_signal;
\t\t\t
\t\t\tassign dummy_signal = dummy_pins[0]; \t//dummy statement
\t\t\t
\t\t\tendmodule
\t\t//************************************************************************************
\tb.\tVHDL
\t\t--************************************************************************************
\t\t\tlibrary ieee;
\t\t\tuse ieee.std_logic_1164.all;
\t\t\t
\t\t\tentity Dummy_IOs is
\t\t\t
\t\t\tport
\t\t\t\t(
\t\t\t\t\tdummy_pins : inout std_logic_vector(3 downto 0)
\t\t\t\t);
\t\t\t
\t\t\tend Dummy_IOs;
\t\t\t
\t\t\tarchitecture rtl of Dummy_IOs is
\t\t\t
\t\t\tsignal dummy_signal : std_logic;
\t\t\t
\t\t\tattribute syn_noprune \t\t: boolean;
\t\t\tattribute syn_force_pads\t: boolean;
\t\t\tattribute syn_noprune of rtl \t: architecture is true;
\t\t\tattribute syn_force_pads of rtl : architecture is true;
\t\t\t
\t\t\t
\t\t\tbegin
\t\t\t\tdummy_signal <= dummy_pins(0) ; -- dummy statement
\t\t\tend rtl;
\t\t--************************************************************************************