Why cannot I pack two registers with the same clock/clock enable/reset signals into one slice after MAP?
Based on Lattice FPGA architecture, two flip flops in a slice share the same clock/clock enable/reset signals. So the two registers can be packed into one slice if their control signals are same. But sometimes if the reset and/or clock enable signals have a large load, they will be duplicated by the synthesis tool to reduce their fanouts. In this case, some registers will have the different duplicated reset and/or clock enable signals. It means any two of them cannot be placed into one slice. In order to prevent the control signal's duplication, the Synplify attribute "syn_maxfan" can be added in the code. Its value can be set big enough and higher than the load number of this control signal , e.g. 10000 as below:
In Verilog:
reg reset /* synthesis syn_maxfan=10000 */;
In VHDL:
attribute syn_maxfan : integer;
attribute syn_maxfan of reset : signal is 10000;
With this attribute, all the registers will have the same control signals. And there is no restriction for any two of them to fit into one slice for the timing and resource utilization purpose.
In addition, the reset signal is often replicated due to its large load. If it can be used as a global reset, the signal duplication issue can be avoided.