LatticeECP3: Why is the SERDES Quad C powered by VCCIB instead of supplying 1.2v, or 1.5v with passive filtering?
The SERDES Quad C of LatticeECP3 FPGA on the Video Protocol board is reserved for HDMI/DVI interface. The HDMI/DVI interface is using TMDS signaling which has a common mode voltage around 3V and a differential swing range of 400-600mV. In order for Lattice CML SERDES to receive HDMI/DVI, the differential input pairs have to be AC-coupled and re-biased to a common mode voltage within the CML limit. And because the TMDS differential swing range is between 400-600mV, if we add the common mode voltage of 1.2V or 1.5V, we violate the maximum allowed voltage for the input buffer of the CML SERDES. Therefore we need to bias the signal swing downward to the required range of the CML input Lbuffer. On the VPB board, we divide the 1.2V or 1.5V by two to get to a common mode voltage of either 0.6V or 0.75V via a pair of 470 ohm resistors to ground. Either 0.6V or 0.75V common mode voltage is within the CML spec.