Platform Manager's CPLD and FPGA sections are logically independent entities. To use the part effectively requires that a design's logic be partitioned in such a way as to take advantage of the unique capabilities of each of these sections.
Logic functions that have any of the following characteristics should typically be implemented in the CPLD sections:
- Control power MOSFET gates directly (no intermediate driver).
- Monitor analog voltages.
- Require high (5V) input or output voltages.
Logic functions that don't have the above characteristics and interface mainly with external CMOS logic should be assigned to the FPGA section. Also, board management logic that requires propagation delays of less than a few microseconds always should be implemented in the FPGA section, as the CPLD logic is designed to operate with microsecond-scale delays.
Because connections between Platform Manager's FPGA and CPLD sections must be made external to the device, it is important to minimize the number of necessary interconnections when partitioning the design. A key to doing this is to keep related logic together. For example, if you have a signal that moves from CPLD to FPGA and back to the CPLD this will usually be more efficiently realized if it is kept entirely within the CPLD.