The Dynamic Clock Selection (DCS) block provided on LatticeSC(M), LatticeEC(P), LatticeEC(P)2, LatticeECP2M, LatticeECP3, LatticeXP, and LatticeXP2 devices is designed to support different flavors of hitless switching which requires a clean handoff from one clock to the other. The DCS works well for this intended application, but in a clock redundancy MUX it is given that the current clock can suddenly stop. The idea is that the MUX would automatically switch to the redundant clock to keep the system up and running. Since the current clock stops the hitless circuitry in the DCS cannot run and the result is the switch never happens.
A redundancy MUX can be implemented using a DCS by utilizing two FPGA Phase-Locked Loops (PLLs). PLLs have the benefit of always providing a toggling clock output even when the input clock stops. The PLL recreates a clock using its internal Voltage Controlled Oscillator (VCO) whose clock will always toggle. Without an input clock the VCO will eventually drift away from the input reference, but it will keep toggling. This toggling is enough for the DCS to switch to the other clock.
Use PLL before each input to the DCS. Place the PLLs in internal feedback mode with a frequency synthesis of 1x. Each PLL acts as a clock buffer for each clock signal. The additional phase offset incurred by using the PLLs is not usually an issue since a DCS is primarily used to source a reference clock in the FPGA.