What do I do if my design with multiple clocks and clock domain transfer does not meet timing anymore?
Prior to ispLever 7.1 release, for a design that contained a clock domain cross transfer from a fast clock to a slow clock, TRACE used the destination (slow) clock period as the constraint. TRACE now uses the fast clock period as the constraint.
This may cause a more pessimistic calculation, which could lead to a decrease in the fMAX reported in the TRACE report file.
The example below shows the clock domain transfer between fast_clk (running at 400 MHz) and slow_clk (running at 140 MHz). In the prior release, TRACE would just use the clock period of the slower clock as the constraint. In ispLever 7.1 and future releases, TRACE calculates the relationship between the faster and slower clock edges to calculate the delay constraint.
Prior releases:
Passed: The following path meets requirements by 2.580ns but exceeds 1.000ns delay constraint requirement for source clock "fast_clk" by 3.562ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q iddr_bt/ud_0 (from fast_clk +)
Destination: FF Data in sw/rdata_par (to slow_clk +)
Delay: 4.479ns (16.5% logic, 83.5% route), 5 logic levels.
Constraint Details:
4.479ns physical path delay din_IOLOGIC to sw/SLICE_173 meets
7.142ns delay constraint less
0.083ns DIN_SET requirement (totaling 7.059ns) by 2.580ns
Physical Path Details:
.....
ispLever 7.1 and later Releases:
Error: The following path exceeds requirements by 2.420ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q iddr_bt/ud_0 (from fast_clk +)
Destination: FF Data in sw/rdata_par (to slow_clk +)
Delay: 4.479ns (16.5% logic, 83.5% route), 5 logic levels.
Constraint Details:
4.479ns physical path delay din_IOLOGIC to sw/SLICE_173 meets
2.142ns delay constraint less
0.083ns DIN_SET requirement (totaling 2.059ns) by 2.420ns
Physical Path Details:
....
This enhancement to the default behavior in TRACE results in a tighter constraint that can be later relaxed if needed. To relax the constraint between the two clock nets, if the design allows, use a multicycle constraint of the form:
MULTICYCLE FROM CLKNET fast_clk TO CLKNET slow_clk 7.142 ns;