In the LatticeSC/M flexiPCS, when the alignment state machine is enabled (enabled via Quad Register Interface register (QIR) 0x04 bit 3 = 0, for 01 or 0123 alignment), the Multi-Channel Aligner (MCA) will continously reset alignment until the MCA finds the set of alignment markers within HIGH_WATERMARK cycles.
In this mode, an mca_aligned_01/23 (or QIR 0x82 bit 0) high indicates that the alignment state machine observed good alignment at the MCA output. When mca_aligned_01/23 (or QIR 0x82 bit 0) goes low, it indicates a problem (including missing alignment characters in one or more of the alignment channels) that prevents the MCA from deskewing the lanes.
For more information, please refer to the LatticeSC/M Family FlexiPCS Data Sheet (DS1005).