Article Details

ID: 1000
Case Type: faq
Category: Architecture
Related To: SERDES/PCS
Family: All FPGA

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LatticeECP2/M /LatticeECP3: How can I implement multiple protocols within a PCS quad (Protocol A RX, Protocol B, TX, etc) ?

For LatticeECP2M devices, all the four channels in a quad must be configured for the same protocol. In LatticeECP3 device family, multiple protocols within one quad of SERDES is supported. The standards are required to have the same reference clock frequency either at the full-rate or half-rate of the supported standards. For example, the following standards with specified data rate can be implemented in a quad.


PCI Express 1.1(2.5Gbps), Gigabit Ethernet(1.25Gbps and 2.5Gbps), SGMII(1.25Gbps), Serial RapidIO Type I(1.25Gbps), Serial RapidIO Type II(2.5Gbps).


In general usage of G8B10B mode or any other user configured mode, the rx and tx of all 4 channels in a quad can use any combination of two data rates, full-rate and half-rate.